Scalable qubit biasing device based on multiplexed charge storage
Embodiments including a semiconductor device circuit for biasing gates of a qubit device as well as a method for operating the device are disclosed. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, where each capacitor is connected between a drain of a respective transistor and ground, where each source of all transistors of all capacitor cells are connected to a common control point, and where each gate of the transistors of the capacitor cells are individually voltage controllable. The embodiment may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternatively activatable.
1 . A semiconductor device circuit for biasing gates of a qubit device comprising:
a multiplexed array of capacitor cells,
wherein each of the capacitor cells comprises a transistor-controlled capacitor;
wherein each of the transistor-controlled capacitors is connected between a drain of a respective transistor and ground;
wherein each source of each of the respective transistors of each of the capacitor cells is connected to a common control point;
wherein each gate of each of the respective transistors of each of the capacitor cells are individually voltage controllable;
a resistor in parallel to the transistor-controlled capacitors of the capacitor cells;
a charging unit connected to the common control point; and
a discharging unit connected to the common control point,
wherein the charging unit and the discharging unit are alternatively activatable.
2 . The semiconductor device circuit according to claim 1 , wherein the charging unit further comprises:
a transistor including a drain connected to the common control point, and further including a source is connected to a supply voltage and a gate connectable to a first control voltage for an activation of the charging unit.
3 . The semiconductor device circuit according to claim 1 , wherein the discharging unit further comprises:
a transistor including a drain, the transistor being connected to the common control point, and further including a source connected via a resistor to ground and a gate connectable to a second control voltage for activation of the discharging unit.
4 . The semiconductor device circuit according to claim 1 , wherein the discharging unit further comprises:
a transistor including a drain connected to the common control point, and further including a source connected via a current measurement unit to ground, and a gate connectable to a third control voltage for activation of the discharging unit.
5 . The semiconductor device circuit according to claim 1 , wherein a voltage level at the drain of each of the respective transistors of each of the capacitor cells are kept quasi-constant by a time-based activation of the gate of each of the respective transistors of each of the capacitor cells.
6 . The semiconductor device circuit according to claim 1 , wherein the semiconductor device circuit is adapted to be operable in a 3K environment.
7 . The semiconductor device circuit according to claim 1 , wherein a signal level at the drain of the transistors of the capacitor cells represents a bias voltage level for a control gate of a qubit device.
8 . The semiconductor device circuit according to claim 1 , wherein a discharging time of the capacitors of the capacitor cells is at least 1000 times larger than a charge time.
9 . The semiconductor device circuit according to claim 1 , wherein each transistor in the semiconductor device circuit is of type n-enhancement.
10 . A method for operating a semiconductor device circuit for biasing gates of a qubit device, the method comprising:
providing a semiconductor device circuit comprising;
a multiplexed array of capacitor cells, wherein each of the capacitor cells comprises a transistor-controlled capacitor, wherein each of the capacitor is connected between a drain of a transistor and ground, wherein each source of the transistors of each of the capacitor cells is connected to a common control point, and wherein each gate of the transistors of the capacitor cells are individually voltage controllable;
a charging unit connected to the common control point; and
a discharging unit connected to the common control point, wherein the charging unit and the discharging unit are alternatively activatable;
activating the discharging unit by connecting a gate of a transistor of the discharging unit to a second control voltage, wherein a source of the transistor of the discharging unit is connected to a supply voltage, and a drain of the transistor of the discharging unit is connected to the common control point;
deactivating the charging unit by connecting a gate of a transistor of the charging unit to ground, wherein a source of the transistor of the charging unit is connected via a discharging unit resistor to a ground, and a drain of the transistor of the charging unit is connected to the common control point; and
activating selectively and time-based one of the capacitor cells of the multiplexed array of capacitor cells.
11 . The method according to claim 10 , further comprising:
activating the charging unit by connecting a gate of a transistor of the charging unit to a first control voltage, wherein a source of the transistor of the charging unit is connected to a supply voltage, and the drain of the transistor of the charging unit is connected to the common control point; and
deactivating the discharging unit by connecting a gate of the transistor of the discharging unit to ground, wherein a source of the transistor of the discharging unit is connected to a supply voltage, and a drain of the transistor of the charging unit is connected to the common control point.
12 . The method according to claim 11 , further comprising:
activating periodically one of the capacitor cells of the multiplexed array of capacitor cells, by applying a recharge voltage to the gate of the transistor of the respective capacitor cells thereby achieving a quasi-constant voltage level at the drain of the transistor of the respective capacitor cells.
13 . The method according to claim 12 , further comprising:
activating periodically another one of the capacitor cells of the multiplexed array of capacitor cells other than the one of the capacitor cells, thereby achieving a quasi-constant voltage level at the drain of the transistor of the another capacitor cell.
14 . The method according to claim 12 , further comprising:
controlling a frequency of an activation of the one of the capacitor cells of the multiplexed array of capacitor cells while leaving a duration of the activation constant to maintain the quasi-constant voltage level at the drain of another one of the capacitor cells of the multiplexed array of capacitor cells.
15 . The method according to claim 10 , further comprising:
measuring a voltage over the discharging unit resistor.
16 . The method according to claim 10 , further comprising:
connecting an output-side resistor in parallel to a capacitor of a capacitor cell; and
activating periodically the respective capacitor cells of the array of capacitor cells, thereby implying a periodic current through the output-side resistor.