Clock selection circuit to output clock signals in response to first and second control signals, display device including the same, and method of driving the same
A clock selection circuit includes: a control circuit to output a first control signal and a second control signal, when at least one scan signal of a previous stage scan signal or a next stage scan signal is input; and a selection circuit to receive clock signals, and output the clock signals when the first control signal and the second control signal are input.
1 . A clock selection circuit comprising:
a control circuit configured to output a first control signal and a second control signal by inverting the first control signal, when at least one scan signal of a previous stage scan signal or a next stage scan signal is input; and
a selection circuit configured to receive clock signals, and output the clock signals when the first control signal and the second control signal are input,
wherein the control circuit is configured to maintain inverted levels of the first control signal and the second control signal during a period in which both the previous stage scan signal and the next stage scan signal are output.
2 . The clock selection circuit according to claim 1 , wherein the control circuit comprises:
a first logic gate configured to:
receive the previous stage scan signal through a first input terminal, and the next stage scan signal through a second input terminal; and
output the first control signal through a first output terminal; and
a second logic gate configured to:
receive the first control signal; and
output the second control signal through a second output terminal by inverting the first control signal.
3 . The clock selection circuit according to claim 2 , wherein the previous stage scan signal and the next stage scan signal have a high level voltage, and
wherein the first logic gate is configured to output a low level of the first control signal by performing a NOR operation on the previous stage scan signal and the next stage scan signal.
4 . The clock selection circuit according to claim 2 , wherein the first logic gate comprises:
a first transistor and a second transistor connected in series with each other between a first power source and a first node; and
a third transistor and a fourth transistor connected in parallel with each other between the first node and a second power source having a voltage lower than that of the first power source, and
wherein the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.
5 . The clock selection circuit according to claim 4 , wherein a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the first input terminal, and
wherein a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to the second input terminal.
6 . The clock selection circuit according to claim 5 , wherein the first logic gate further comprises a third input terminal configured to receive a current stage scan signal.
7 . The clock selection circuit according to claim 6 , wherein the first logic gate further comprises:
a fifth transistor connected in series to the first transistor and the second transistor between the first power source and the first node; and
a sixth transistor connected in parallel to the third transistor and the fourth transistor between the first node and the second power source, and
wherein the fifth transistor is a P-type transistor and the sixth transistor is an N-type transistor.
8 . The clock selection circuit according to claim 7 , wherein a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the third input terminal.
9 . The clock selection circuit according to claim 2 , wherein the second logic gate is an inverter configured to output the second control signal by inverting the first control signal.
10 . The clock selection circuit according to claim 9 , wherein the second logic gate comprises a P-type first transistor and an N-type second transistor that are connected in series with each other between a first power source and a second power source having a voltage lower than that of the first power source, and
wherein a gate electrode of the P-type first transistor and a gate electrode of the N-type second transistor are connected to the first output terminal, and a common node between the P-type first transistor and the N-type second transistor is connected to the second output terminal.
11 . The clock selection circuit according to claim 1 , wherein the selection circuit comprises:
a first transmission gate connected between a first clock input terminal and a first clock output terminal, the first clock input terminal being configured to receive a first clock signal, and the first transmission gate being configured to be turned on when the first control signal and the second control signal are input; and
a second transmission gate connected between a second clock input terminal and a second clock output terminal, the second clock input terminal being configured to receive a second clock signal, and the second transmission gate being configured to be turned on when the first control signal and the second control signal are input.
12 . The clock selection circuit according to claim 11 , wherein the first transmission gate comprises a P-type first control transistor and an N-type second control transistor that are connected in parallel with each other between the first clock input terminal and the first clock output terminal, and
wherein the P-type first control transistor is configured to be turned on when the first control signal is input, and the N-type second control transistor is configured to be turned on when the second control signal is input.
13 . The clock selection circuit according to claim 11 , wherein the second transmission gate comprises a P-type first control transistor and an N-type second control transistor that are connected in parallel with each other between the second clock input terminal and the second clock output terminal, and
wherein the P-type first control transistor is configured to be turned on when the first control signal is input, and the N-type second control transistor is configured to be turned on when the second control signal is input.
14 . A display device comprising:
pixels connected to scan lines and data lines;
a scan driver configured to supply a scan signal to the scan lines;
a clock controller configured to sequentially output a first control signal and a second control signal by inverting the first control signal in a horizontal line unit in response to the scan signal sequentially input in the horizontal line unit; and
a clock selector configured to receive clock signals for driving the scan driver, and supply the clock signals to the scan driver in the horizontal line unit in response to the first control signal and the second control signal,
wherein the clock controller is configured to maintain inverted levels of the first control signal and the second control signal during a period in which both a previous scan signal and a next scan signal of the scan signal are output.
15 . The display device according to claim 14 , wherein the scan driver comprises a stage circuit located for each horizontal line,
wherein the clock controller comprises a control circuit located for each horizontal line, and
wherein the clock selector comprises a selection circuit located for each horizontal line.
16 . The display device according to claim 15 , wherein a stage circuit of a first horizontal line is configured to receive a scan start signal, and
wherein a control circuit of the first horizontal line is configured to receive a clock start signal overlapping with the scan start signal.
17 . The display device according to claim 15 , wherein a control circuit of a last horizontal line is configured to receive an end signal overlapping with a scan signal corresponding to the last horizontal line during a partial period.
18 . The display device according to claim 15 , wherein an i-th control circuit of an i-th horizontal line is configured to output the first control signal and the second control signal in response to the previous scan signal of a previous horizontal line and the next scan signal of a next horizontal line, where i is a natural number.
19 . The display device according to claim 18 , wherein the i-th control circuit comprises:
a first logic gate configured to generate the first control signal by performing a NOR operation on the previous scan signal and the next scan signal; and
a second logic gate configured to generate the second control signal by inverting the first control signal.
20 . The display device according to claim 15 , wherein an i-th control circuit of an i-th horizontal line is configured to output the first control signal and the second control signal in response to the previous scan signal of a previous horizontal line, a current scan signal of a current horizontal line, and the next scan signal of a next horizontal line, where i is a natural number.
21 . The display device according to claim 20 , wherein the i-th control circuit comprises:
a first logic gate configured to generate the first control signal by performing a NOR operation on the previous scan signal, the current scan signal, and the next scan signal; and
a second logic gate configured to generate the second control signal by inverting the first control signal.
22 . The display device according to claim 15 , wherein an i-th selection circuit of an i-th horizontal line is configured to receive a first clock signal and a second clock signal, and supply the first clock signal and the second clock signal to an i-th stage circuit of the i-th horizontal line when an i-th first control signal and an i-th second control signal are input from an i-th control circuit of the i-th horizontal line, where i is a natural number.
23 . The display device according to claim 22 , wherein the i-th selection circuit comprises:
a first transmission gate configured to receive the first clock signal, and supply the first clock signal to the i-th stage circuit by being turned on when the i-th first control signal and the i-th second control signal are supplied; and
a second transmission gate configured to receive the second clock signal, and supply the second clock signal to the i-th stage circuit by being turned on when the i-th first control signal and the i-th second control signal are supplied.
24 . The display device according to claim 23 , wherein the i-th stage circuit comprises a transmission gate configured to be turned on and turned off in response to the first clock signal and the second clock signal.
25 . A method of driving a display device, the method comprising:
sequentially generating a scan signal in a scan driver;
sequentially generating a first control signal and a second control signal by inverting the first control signal in a clock controller in response to the scan signal; and
sequentially supplying clock signals used for generating the scan signal from a clock selector to the scan driver in response to the first control signal and the second control signal,
wherein inverted levels of the first control signal and the second control signal are maintained by the clock controller during a period in which both a previous stage scan signal and a next stage scan signal of the scan signal are output.
26 . The method according to claim 25 , wherein the clock controller generates a first-first control signal and a first-second control signal corresponding to a first horizontal line in response to a clock start signal overlapping with a scan start signal supplied to the scan driver.