Display panel and display device

1 . A display panel, comprising a plurality of gate driving circuits in a cascaded configuration, wherein each of the plurality of gate driving circuits comprises:

a pull-up module electrically connected to a first node, wherein the pull-up module is configured, according to a potential of the first node, to connect a clock signal line to a signal output terminal of a current stage of gate driving circuit, or to disconnect an electrical connection between the clock signal line and the signal output terminal;

a pull-down maintaining module electrically connected to the first node and a low-potential power supply terminal;

an inverting module, wherein one end of the inverting module is electrically connected directly to the first node, the other end of the inverting module is electrically connected directly to the pull-down maintaining module at a second node, and the inverting module is configured, according to the potential of the first node, for controlling the pull-down maintaining module to connect the low-potential power supply terminal with the first node, or to disconnect an electrical connection between the low-potential power supply terminal and the first node; and

a pull-down capacitor, wherein at least one of the first node and the second node is electrically connected directly to a first electrode plate of the pull-down capacitor, and a second electrode plate of the pull-down capacitor is electrically connected directly to the low-potential power supply terminal.

2 . The display panel according to claim 1 , wherein the first electrode plate of the pull-down capacitor is electrically connected to the second node, and the second electrode plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal.

3 . The display panel according to claim 1 , wherein the first electrode plate of the pull-down capacitor is electrically connected to the first node, and the second electrode plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal.

4 . The display panel according to claim 1 , wherein the pull-down capacitor comprises a first sub-capacitor and a second sub-capacitor, a first electrode plate of the first sub-capacitor is electrically connected to the first node, a second electrode plate of the first sub-capacitor is electrically connected to the low-potential power supply terminal, a first electrode plate of the second sub-capacitor is electrically connected to the second node, and a second electrode plate of the second sub-capacitor is electrically connected to the low-potential power supply terminal.

5 . The display panel according to claim 4 , wherein the pull-down maintaining module comprises:

a first pull-down maintaining transistor, wherein a gate of the first pull-down maintaining transistor is electrically connected to the second node, a first electrode of the first pull-down maintaining transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the first pull-down maintaining transistor is electrically connected to the signal output terminal; and

a second pull-down maintaining transistor, wherein a gate of the second pull-down maintaining transistor is electrically connected to the second node, a first electrode of the second pull-down maintaining transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second pull-down maintaining transistor is electrically connected to the first node;

wherein the first electrode plate of the second sub-capacitor is electrically connected to the gate of the first pull-down maintaining transistor and the gate of the second pull-down maintaining transistor.

6 . The display panel according to claim 5 , wherein the inverting module comprises:

a first inverting transistor, wherein a gate of the first inverting transistor is electrically connected to a high-potential power supply terminal, and a first electrode of the first inverting transistor is electrically connected to the high-potential power supply terminal;

a second inverting transistor, wherein a gate of the second inverting transistor is electrically connected to the first node, a first electrode of the second inverting transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second inverting transistor is electrically connected to a second electrode of the first inverting transistor at a third node;

a third inverting transistor, wherein a gate of the third inverting transistor is electrically connected to the second electrode of the first inverting transistor at the third node, a first electrode of the third inverting transistor is electrically connected to the high-potential power supply terminal, and a second electrode of the third inverting transistor is electrically connected to the pull-down maintaining module at the second node; and

a fourth inverting transistor, wherein a gate of the fourth inverting transistor is electrically connected to the first node, a first electrode of the fourth inverting transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the fourth inverting transistor is electrically connected to the second node;

wherein the first electrode plate of the first sub-capacitor is electrically connected to the gate of the second inverting transistor and the gate of the fourth inverting transistor.

7 . The display panel according to claim 6 , further comprising:

a substrate;

a gate layer disposed on a side of the substrate, wherein the gate layer comprises the gate of the first pull-down maintaining transistor, the gate of the second pull-down maintaining transistor, the gate of the second inverting transistor, the gate of the fourth inverting transistor, the first electrode plate of the first sub-capacitor, and the first electrode plate of the second sub-capacitor; and

a source/drain layer disposed on a side of the gate layer away from the substrate, wherein the source/drain layer comprises the first electrode of the first pull-down maintaining transistor, the first electrode of the second pull-down maintaining transistor, the first electrode of the second inverting transistor, the first electrode of the fourth inverting transistor, the second electrode plate of the first sub-capacitor, and the second electrode plate of the second sub-capacitor;

wherein the gate of the first pull-down maintaining transistor and the gate of the second pull-down maintaining transistor are connected to the first electrode plate of the second sub-capacitor, and the first electrode of the first pull-down maintaining transistor and the first electrode of the second pull-down maintaining transistor are connected to the second electrode plate of the second sub-capacitor; and/or

wherein the gate of the second inverting transistor and the gate of the fourth inverting transistor are connected to the first electrode plate of the first sub-capacitor, and the first electrode of the second inverting transistor and the first electrode of the fourth inverting transistor are connected to the second electrode plate of the first sub-capacitor.

8 . The display panel according to claim 7 , further comprising:

a pixel conductive layer disposed on a side of the source/drain layer away from the gate layer;

wherein the pixel conductive layer is electrically connected to at least one of the gate of the first pull-down maintaining transistor, the gate of the second pull-down maintaining transistor, the gate of the second inverting transistor, and the gate of the fourth inverting transistor.

9 . The display panel according to claim 8 , wherein the pixel conductive layer comprises a first transparent conductive portion and a second transparent conductive portion, the first transparent conductive portion is connected to the gate of the first pull-down maintaining transistor and the gate of the second pull-down maintaining transistor, and the second transparent conductive portion is connected to the gate of the second inverting transistor and the gate of the fourth inverting transistor.

10 . The display panel according to claim 6 , wherein the second electrode plate of the first sub-capacitor is located between the first electrode of the second inverting transistor and the first electrode of the fourth inverting transistor.

11 . The display panel according to claim 5 , wherein the first electrode of the first pull-down maintaining transistor comprises a first branch electrode and a second branch electrode, the first branch electrode and the second branch electrode are arranged along a first direction, a length of the first branch electrode along a second direction is greater than a length of the second branch electrode along the second direction, and the second electrode plate of the second sub-capacitor and a part of the first branch electrode extending beyond the second branch electrode are arranged along the first direction; and

wherein in the second direction, the second electrode plate of the second sub-capacitor is located between the second branch electrode and the first electrode of the second pull-down maintaining transistor, and an included angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees.

12 . The display panel according to claim 1 , wherein each of the plurality of gate driving circuits comprises:

a pull-up control module comprising a pull-up control transistor, wherein a gate of the pull-up control transistor and a first electrode of the pull-up control transistor are configured to receive a pull-up control signal, and a second electrode of the pull-up control transistor is electrically connected to the first node;

a pull-down module comprising a first pull-down transistor and a second pull-down transistor, wherein a gate of the first pull-down transistor is configured to receive a first pull-down control signal, a first electrode of the first pull-down transistor is electrically connected to the low-potential power supply terminal, a second electrode of the first pull-down transistor is electrically connected to the signal output terminal, a gate of the second pull-down transistor is configured to receive a second pull-down control signal, a first electrode of the second pull-down transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second pull-down transistor is electrically connected to the first node;

a reset module comprising a first reset transistor and a second reset transistor, wherein a gate of the first reset transistor is connected to a reset signal line, a first electrode of the first reset transistor is electrically connected to the low-potential power supply terminal, a second electrode of the first reset transistor is electrically connected to the signal output terminal, a gate of the second reset transistor is connected to the reset signal line, a first electrode of the second reset transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second reset transistor is electrically connected to the first node; and

a storage capacitor, wherein one electrode plate of the storage capacitor is electrically connected to the first node, and the other electrode plate of the storage capacitor is electrically connected to the signal output terminal.

13 . A display device, comprising a display panel, wherein the display panel comprises a plurality of gate driving circuits in a cascaded configuration, and each of the plurality of gate driving circuits comprises:

a pull-up module electrically connected to a first node, wherein the pull-up module is configured, according to a potential of the first node, to connect a clock signal line to a signal output terminal of a current stage of gate driving circuit, or to disconnect an electrical connection between the clock signal line and the signal output terminal;

a pull-down maintaining module electrically connected to the first node and a low-potential power supply terminal;

an inverting module, wherein one end of the inverting module is electrically connected directly to the first node, the other end of the inverting module is electrically connected directly to the pull-down maintaining module at a second node, and the inverting module is configured, according to the potential of the first node, for controlling the pull-down maintaining module to connect the low-potential power supply terminal with the first node, or to disconnect an electrical connection between the low-potential power supply terminal and the first node; and

a pull-down capacitor, wherein at least one of the first node and the second node is electrically connected directly to a first electrode plate of the pull-down capacitor, and a second electrode plate of the pull-down capacitor is electrically connected directly to the low-potential power supply terminal.

14 . The display device according to claim 13 , wherein the first electrode plate of the pull-down capacitor is electrically connected to the second node, and the second electrode plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal.

15 . The display device according to claim 13 , wherein the first electrode plate of the pull-down capacitor is electrically connected to the first node, and the second electrode plate of the pull-down capacitor is electrically connected to the low-potential power supply terminal.

16 . The display device according to claim 13 , wherein the pull-down capacitor comprises a first sub-capacitor and a second sub-capacitor, a first electrode plate of the first sub-capacitor is electrically connected to the first node, a second electrode plate of the first sub-capacitor is electrically connected to the low-potential power supply terminal, a first electrode plate of the second sub-capacitor is electrically connected to the second node, and a second electrode plate of the second sub-capacitor is electrically connected to the low-potential power supply terminal.

17 . The display device according to claim 16 , wherein the pull-down maintaining module comprises:

a first pull-down maintaining transistor, wherein a gate of the first pull-down maintaining transistor is electrically connected to the second node, a first electrode of the first pull-down maintaining transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the first pull-down maintaining transistor is electrically connected to the signal output terminal; and

a second pull-down maintaining transistor, wherein a gate of the second pull-down maintaining transistor is electrically connected to the second node, a first electrode of the second pull-down maintaining transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second pull-down maintaining transistor is electrically connected to the first node;

wherein the first electrode plate of the second sub-capacitor is electrically connected to the gate of the first pull-down maintaining transistor and the gate of the second pull-down maintaining transistor.

18 . The display device according to claim 17 , wherein the inverting module comprises:

a first inverting transistor, wherein a gate of the first inverting transistor is electrically connected to a high-potential power supply terminal, and a first electrode of the first inverting transistor is electrically connected to the high-potential power supply terminal;

a second inverting transistor, wherein a gate of the second inverting transistor is electrically connected to the first node, a first electrode of the second inverting transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the second inverting transistor is electrically connected to a second electrode of the first inverting transistor at a third node;

a third inverting transistor, wherein a gate of the third inverting transistor is electrically connected to the second electrode of the first inverting transistor at the third node, a first electrode of the third inverting transistor is electrically connected to the high-potential power supply terminal, and a second electrode of the third inverting transistor is electrically connected to the pull-down maintaining module at the second node; and

a fourth inverting transistor, wherein a gate of the fourth inverting transistor is electrically connected to the first node, a first electrode of the fourth inverting transistor is electrically connected to the low-potential power supply terminal, and a second electrode of the fourth inverting transistor is electrically connected to the second node;

wherein the first electrode plate of the first sub-capacitor is electrically connected to the gate of the second inverting transistor and the gate of the fourth inverting transistor.

19 . The display device according to claim 18 , wherein the display panel further comprises:

a substrate;

a gate layer disposed on a side of the substrate, wherein the gate layer comprises the gate of the first pull-down maintaining transistor, the gate of the second pull-down maintaining transistor, the gate of the second inverting transistor, the gate of the fourth inverting transistor, the first electrode plate of the first sub-capacitor, and the first electrode plate of the second sub-capacitor; and

a source/drain layer disposed on a side of the gate layer away from the substrate, wherein the source/drain layer comprises the first electrode of the first pull-down maintaining transistor, the first electrode of the second pull-down maintaining transistor, the first electrode of the second inverting transistor, the first electrode of the fourth inverting transistor, the second electrode plate of the first sub-capacitor, and the second electrode plate of the second sub-capacitor;

wherein the gate of the first pull-down maintaining transistor and the gate of the second pull-down maintaining transistor are connected to the first electrode plate of the second sub-capacitor, and the first electrode of the first pull-down maintaining transistor and the first electrode of the second pull-down maintaining transistor are connected to the second electrode plate of the second sub-capacitor; and/or

wherein the gate of the second inverting transistor and the gate of the fourth inverting transistor are connected to the first electrode plate of the first sub-capacitor, and the first electrode of the second inverting transistor and the first electrode of the fourth inverting transistor are connected to the second electrode plate of the first sub-capacitor.

20 . The display device according to claim 17 , wherein the first electrode of the first pull-down maintaining transistor comprises a first branch electrode and a second branch electrode, the first branch electrode and the second branch electrode are arranged along a first direction, a length of the first branch electrode along a second direction is greater than a length of the second branch electrode along the second direction, and the second electrode plate of the second sub-capacitor and a part of the first branch electrode extending beyond the second branch electrode are arranged along the first direction; and

wherein in the second direction, the second electrode plate of the second sub-capacitor is located between the second branch electrode and the first electrode of the second pull-down maintaining transistor, and an included angle between the first direction and the second direction is greater than 0 degrees and less than or equal to 90 degrees.