IP Library › Granted Patent US 12670843
Granted Patent B2
US 12670843 · App. 18/223,792 · Granted Jun 30, 2026

Array substrate, display panel and display device

Inventors: Chao Yu (Wuhan, CN); Fei Li (Wuhan, CN)
Assignee: Wuhan Tianma Microelectronics Co., Ltd.
G09G3/32G09G3/3233H10D86/441H10D86/60H10K59/131G09G2300/0426G09G2300/0819G09G2300/0842G09G2300/0861G09G2310/0267
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Quick Facts
Patent No.
US 12670843
App. No.
18/223,792
Granted
Jun 30, 2026
Kind
B2
Abstract

Provided are an array substrate, a display panel, and a display device. The array substrate includes a substrate, multiple pixel driving circuits, and multiple signal lines; a pixel driving circuit of the multiple pixel driving circuits includes a drive transistor and a regulating transistor, the multiple signal lines include a scan signal line, a regulating signal line, and a power signal line, and the scan signal line includes a regulating control signal line; a first electrode of the drive transistor is electrically connected to a power signal line; a first electrode of the regulating transistor is electrically connected to the regulating signal line, a second electrode of the regulating transistor is electrically connected to the first electrode of the drive transistor or a second electrode of the drive transistor, and the gate of the regulating transistor is electrically connected to the regulating control signal line.

Claims (68)

1 . An array substrate, comprising: a substrate, a plurality of pixel driving circuits, and a plurality of signal lines, wherein the plurality of pixel driving circuits and the plurality of signal lines are located on a same side of the substrate;

a pixel driving circuit of the plurality of pixel driving circuits comprises a drive transistor and a regulating transistor, the plurality of signal lines comprise a scan signal line, a regulating signal line, and a power signal line, and the scan signal line comprises a regulating control signal line;

a first electrode of the drive transistor is electrically connected to the power signal line;

a first electrode of the regulating transistor is electrically connected to the regulating signal line, a second electrode of the regulating transistor is electrically connected to the first electrode of the drive transistor or a second electrode of the drive transistor, and a gate of the regulating transistor is electrically connected to the regulating control signal line;

the scan signal line extends in a first direction, the regulating signal line extends in a second direction, the regulating signal line is disposed in a layer different from a layer where the scan signal line is disposed, and the first direction and the second direction intersect each other;

the plurality of signal lines further comprise a data line extending in the second direction; and

the pixel driving circuit further comprises a data write transistor, wherein a first electrode of the data write transistor is electrically connected to the data line, and a second electrode of the data write transistor is electrically connected to the first electrode of the drive transistor.

2 . The array substrate of claim 1 , further comprising: connection lines comprising a first connection line and a second connection line, wherein the first connection line is electrically connected to the second connection line, the first connection line extends in the first direction, and the second connection line extends in the second direction;

and

the first connection line connects the data line and the second connection line, and the first connection line is disposed in a layer different from a layer where the data line is disposed and a layer where the regulating signal line is disposed.

3 . The array substrate of claim 2 , wherein the second connection line is disposed in a layer same as the layer where the data line is disposed.

4 . The array substrate of claim 3 , wherein a layer where the first connection line is disposed is located between the layer where the data line is disposed and the substrate.

5 . The array substrate of claim 4 , wherein the layer where the first connection line is disposed is located between the layer where the regulating signal line is disposed and the substrate.

6 . The array substrate of claim 5 , wherein the plurality of signal lines further comprise a reset signal line extending in the first direction, wherein a layer where the reset signal line is disposed is located between the layer where the scan signal line is disposed and the layer where the regulating signal line is disposed; and

the first connection line is disposed in a layer same as the layer where the reset signal line is disposed.

7 . The array substrate of claim 6 , wherein the scan signal line further comprises a light-emitting control scan signal line;

the pixel driving circuit further comprises a power write transistor;

a first electrode of the power write transistor is electrically connected to the power signal line, a second electrode of the power write transistor is electrically connected to the first electrode of the drive transistor, and a gate of the power write transistor is electrically connected to the light-emitting control scan signal line; and

an area where the pixel driving circuit is disposed is a pixel area, and in a same pixel area, the first connection line is located between the reset signal line and the light-emitting control scan signal line.

8 . The array substrate of claim 5 , further comprising: a first jumper, wherein the first jumper is disposed in a layer different from both the layer where the data line is disposed and the layer where the first connection line is disposed, a first terminal of the first jumper is electrically connected to the data line through a via, and a second terminal of the first jumper is electrically connected to the first connection line through the via.

9 . The array substrate of claim 8 , wherein the first jumper is disposed in a layer same as the layer where the regulating signal line is disposed.

10 . The array substrate of claim 4 , wherein the layer where the first connection line is disposed is located on a side of the layer where the regulating signal line is disposed, which faces away from the substrate.

11 . The array substrate of claim 10 , wherein the layer where the first connection line is disposed is located between the layer where the regulating signal line is disposed and the layer where the data line is disposed.

12 . The array substrate of claim 3 , wherein a layer where the first connection line is disposed is on a side of the layer where the data line is disposed, which faces away from the substrate.

13 . The array substrate of claim 3 , wherein the power signal line comprises a first power signal line and a second power signal line, wherein the first power signal line is electrically connected to the second power signal line, the first power signal line extends in the first direction, the second power signal line extends in the second direction, and the second power signal line is disposed in a layer same as the layer where the data line is disposed and a layer where the second connection line is disposed;

the scan signal line further comprises a light-emitting control scan signal line; the pixel driving circuit further comprises a light-emitting control transistor, wherein a first electrode of the light-emitting control transistor is electrically connected to the second electrode of the drive transistor, a second electrode of the light-emitting control transistor is electrically connected to a light-emitting element through a via, and a gate of the light-emitting control transistor is electrically connected to the light-emitting control scan signal line; and

an area where the pixel driving circuit is located is a pixel area, and in a same pixel area, in the first direction, the second connection line is located on a side of the second power signal line, which faces away from the substrate.

14 . The array substrate of claim 2 , wherein the second connection line is disposed in a layer different from the layer where the data line is disposed.

15 . The array substrate of claim 14 , wherein a layer where the second connection line is disposed is located on a side of the layer where the data line is disposed, which faces away from the substrate.

16 . The array substrate of claim 14 , wherein the first connection line is disposed in a layer same as the layer where the second connection line is disposed.

17 . The array substrate of claim 14 , wherein the power signal line comprises a first power signal line and a second power signal line, wherein the first power signal line is electrically connected to the second power signal line, the first power signal line extends in the first direction, the second power signal line extends in the second direction, and the second power signal line is disposed in a layer same as the layer where the data line is disposed; and

in a direction perpendicular to a plane where the substrate is located, the second connection line and the second power signal line overlap.

18 . The array substrate of claim 2 , wherein the layer where the regulating signal line is disposed is located between a layer where the second connection line is disposed and the substrate, and is located between the layer where the data line is disposed and the substrate.

19 . The array substrate of claim 2 , wherein the regulating signal line is disposed in a layer same as a layer where the second connection line is disposed and the layer where the data line is disposed.

20 . The array substrate of claim 2 , wherein the regulating signal line is disposed in a layer same as the layer where the data line is disposed, and the layer where the regulating signal line is disposed is located between a layer where the second connection is disposed and the substrate.

21 . The array substrate of claim 2 , wherein the regulating signal line is located on a side of the data line, which faces away from the substrate; and the second connection line is disposed in a layer same as the layer where the data line is disposed.

22 . The array substrate of claim 2 , wherein the plurality of signal lines further comprise a reset signal line extending in the first direction, wherein a layer where the reset signal line is disposed is located between the layer where the scan signal line is disposed and the layer where the regulating signal line is disposed; and

in a direction perpendicular to a plane where the substrate is located, the first connection line is disposed in a layer different from the layer where the reset signal line is disposed, and the first connection line and the reset signal line at least partially overlap.

23 . The array substrate of claim 2 , wherein the plurality of signal lines further comprise an auxiliary reset signal line extending in the second direction, wherein the auxiliary reset signal line is disposed in a layer same as the layer where the regulating signal line is disposed; and

in a direction perpendicular to a plane where the substrate is located, the second connection line is disposed in a layer different from a layer where the auxiliary reset signal line is disposed, and the second connection line and the auxiliary reset signal line overlap.

24 . The array substrate of claim 2 , wherein the regulating signal line comprises a first line segment extending in the second direction, wherein in a direction perpendicular to a plane where the substrate is located, the first line segment and the data line overlap.

25 . The array substrate of claim 2 , wherein in the first direction, one second connection line is disposed between two adjacent data lines, and one data line is disposed between two adjacent second connection lines.

26 . The array substrate of claim 2 , wherein the first connection line is electrically connected to the data line through a via; and

the array substrate further comprises a dummy via, wherein the dummy via is located at an intersection of the first connection line and the data line.

27 . The array substrate of claim 1 , wherein the power signal line comprises a first power signal line and a second power signal line, wherein the first power signal line is electrically connected to the second power signal line, the first power signal line extends in the first direction, and the second power signal line extends in the first direction; and

in a direction perpendicular to a plane where the substrate is located, the first power signal line is disposed in a layer different from a layer where the second power signal line is disposed, and the first power signal line and the second power signal line overlap.

28 . The array substrate of claim 1 , wherein the power signal line comprises a first power signal line and a second power signal line, wherein the first power signal line is electrically connected to the second power signal line, the first power signal line extends in the first direction, a layer where the first power signal line is disposed is located between a layer where the second power signal line is disposed and the substrate;

the second power signal line comprises a second power signal line body portion and a second power signal line extension portion, wherein an extension direction of the second power signal line body portion and an extension direction of the second power signal line extension portion intersect each other;

the plurality of signal lines further comprise a data line and a reset signal line, and the scan signal line further comprises a first scan signal line and a second scan signal line; and the pixel driving circuit further comprises a first reset transistor;

a first electrode of the first reset transistor is electrically connected to the reset signal line, a second electrode of the first reset transistor is electrically connected to a gate of the drive transistor, and a gate of the first reset transistor is electrically connected to the first scan signal line;

a gate of the data write transistor is electrically connected to the second scan signal line; and

in the second direction, a semiconductor layer located between the first scan signal line and the second scan signal line is denoted as a first node semiconductor layer; and in a direction perpendicular to a plane where the substrate is located, the second power signal line extension portion is disposed in a same layer as a layer where the first node semiconductor layer is disposed, and the second power signal line extension portion and the first node semiconductor layer overlap.

29 . A display panel, comprising: an array substrate and a plurality of light-emitting elements disposed on the array substrate;

wherein the array substrate comprises: a substrate, a plurality of pixel driving circuits, and a plurality of signal lines, wherein the plurality of pixel driving circuits and the plurality of signal lines are located on a same side of the substrate;

a pixel driving circuit of the plurality of pixel driving circuits comprises a drive transistor and a regulating transistor, the plurality of signal lines comprise a scan signal line, a regulating signal line, and a power signal line, and the scan signal line comprises a regulating control signal line;

a first electrode of the drive transistor is electrically connected to the power signal line;

a first electrode of the regulating transistor is electrically connected to the regulating signal line, a second electrode of the regulating transistor is electrically connected to the first electrode of the drive transistor or a second electrode of the drive transistor, and a gate of the regulating transistor is electrically connected to the regulating control signal line;

the scan signal line extends in a first direction, the regulating signal line extends in a second direction, the regulating signal line is disposed in a layer different from a layer where the scan signal line is disposed, and the first direction and the second direction intersect each other;

the plurality of signal lines further comprise a data line extending in the second direction; and

the pixel driving circuit further comprises a data write transistor, wherein a first electrode of the data write transistor is electrically connected to the data line, and a second electrode of the data write transistor is electrically connected to the first electrode of the drive transistor.

30 . A display device, comprising: a display panel, wherein the display panel comprises: an array substrate and a plurality of light-emitting elements disposed on the array substrate;

wherein the array substrate comprises: a substrate, a plurality of pixel driving circuits, and a plurality of signal lines, wherein the plurality of pixel driving circuits and the plurality of signal lines are located on a same side of the substrate;

a pixel driving circuit of the plurality of pixel driving circuits comprises a drive transistor and a regulating transistor, the plurality of signal lines comprise a scan signal line, a regulating signal line, and a power signal line, and the scan signal line comprises a regulating control signal line;

a first electrode of the drive transistor is electrically connected to the power signal line;

a first electrode of the regulating transistor is electrically connected to the regulating signal line, a second electrode of the regulating transistor is electrically connected to the first electrode of the drive transistor or a second electrode of the drive transistor, and a gate of the regulating transistor is electrically connected to the regulating control signal line;

the scan signal line extends in a first direction, the regulating signal line extends in a second direction, the regulating signal line is disposed in a layer different from a layer where the scan signal line is disposed, and the first direction and the second direction intersect each other;

the plurality of signal lines further comprise a data line extending in the second direction; and

the pixel driving circuit further comprises a data write transistor, wherein a first electrode of the data write transistor is electrically connected to the data line, and a second electrode of the data write transistor is electrically connected to the first electrode of the drive transistor.