Tiled display panel
A tiled display panel is provided. The tiled display panel includes multiple substrates, multiple liquid crystal pixels, multiple LED pixels, and multiple light-emitting circuits. Each substrate has a display region and a boundary region. The boundary region is located between the display region and the tiled boundary tiled by the substrates. The liquid crystal pixels are arranged in an array in the display region. The LED pixels are arranged in series in the boundary region. The light-emitting circuits are arranged in series in the boundary region along a first direction and are electrically connected to the LED pixels to provide multiple light-emitting signals for the LED pixels.
1 . A tiled display panel, comprising:
a plurality of substrates, wherein each of the plurality of substrates has a display region and at least one boundary region, and the at least one boundary region is respectively located between the display region and a tiled boundary tiled by the plurality of substrates;
a plurality of liquid crystal pixels, arranged in an array in the display region;
a plurality of light-emitting diode (LED) pixels, arranged in an array in the at least one boundary region;
a plurality of light-emitting circuits, arranged in series in the at least one boundary region along a first direction and electrically connected to the plurality of LED pixels to provide a plurality of light-emitting signals for the plurality of LED pixels;
a plurality of first gate lines, spanning the display region along the first direction and receiving a plurality of gate signals; and
a plurality of second gate lines, spanning the display region and the at least one boundary region along a second direction perpendicular to the first direction, wherein each of the plurality of second gate lines is electrically connected to one or part of the plurality of first gate lines, part of the plurality of liquid crystal pixels, and part of the plurality of LED pixels.
2 . The tiled display panel according to claim 1 , wherein the plurality of light-emitting circuits are arranged in series between the plurality of LED pixels and the tiled boundary.
3 . The tiled display panel according to claim 1 , further comprising:
a plurality of first break over lines, electrically connected to one of the plurality of second gate lines respectively, and extending along the first direction respectively to be electrically connected to a first-level light-emitting circuit and a next-level light-emitting circuit of the plurality of light-emitting circuits.
4 . The tiled display panel according to claim 3 , wherein a configuration direction of the first-level light-emitting circuit relative to the second gate line electrically connected to each of the plurality of first break over lines is opposite to a configuration direction of the next-level light-emitting circuit relative to the second gate line electrically connected to each of the plurality of first break over lines.
5 . The tiled display panel according to claim 1 , further comprising:
a plurality of second break over lines, electrically connected to one of the plurality of second gate lines respectively, and extending along the first direction to be electrically connected to a first-level light-emitting circuit of the plurality of light-emitting circuits respectively; and
a plurality of third gate lines, spanning the display region and the at least one boundary region along the second direction, wherein each of the plurality of third gate lines is located between two adjacent second gate lines and is electrically connected to one of the plurality of first gate lines and one of the plurality of light-emitting circuits, and the first gate line electrically connected to each of the third gate lines is closer to the at least one boundary region than the first gate line electrically connected to the plurality of adjacent second gate lines.
6 . The tiled display panel according to claim 1 , further comprising:
a plurality of third break over lines, electrically connected to one of the plurality of second gate lines respectively, and extending along the first direction to be electrically connected to a next-level light-emitting circuit of the plurality of light-emitting circuits respectively; and
a plurality of fourth gate lines, spanning the display region and the at least one boundary region along the second direction, wherein each of the plurality of fourth gate lines is located between two adjacent second gate lines and is electrically connected to one of the plurality of first gate lines and one of the plurality of light-emitting circuits, and the first gate line electrically connected to each of the plurality of fourth gate lines is further away from the at least one boundary region than the first gate lines electrically connected to the plurality of adjacent second gate lines.
7 . The tiled display panel according to claim 1 , further comprising:
a plurality of fifth gate lines, spanning the display region and the at least one boundary region along the second direction, wherein each of the plurality of fifth gate lines is located between two adjacent second gate lines and is electrically connected to one of the plurality of first gate lines and one of the plurality of light-emitting circuits, and the first gate line electrically connected to each of the fifth gate lines is closer to the at least one boundary region than the plurality of first gate lines electrically connected to the plurality of adjacent second gate lines; and
a plurality of sixth gate lines, spanning the display region and the at least one boundary region along the second direction, wherein each of the plurality of sixth gate lines is located between two adjacent second gate lines and is electrically connected to one of the plurality of first gate lines and one of the plurality of light-emitting circuits, and the first gate line electrically connected to each of the plurality of sixth gate lines is further away from the at least one boundary region than the plurality of first gate lines electrically connected to the plurality of adjacent second gate lines.
8 . The tiled display panel according to claim 1 , wherein each of the plurality of liquid crystal pixels comprises:
a switch transistor, having a first terminal receiving a pixel data voltage, a control terminal receiving a first gate signal of the plurality of gate signals, and a second terminal;
a first pixel capacitance, coupled between the second terminal of the switch transistor and a first common terminal; and
a second pixel capacitance, coupled between the second terminal of the switch transistor and a second common terminal.
9 . The tiled display panel according to claim 1 , wherein each of the plurality of LED pixels comprises:
a light-emitting diode (LED), having an anode and a cathode receiving a system low voltage;
a first transistor, having a first terminal receiving a pixel data voltage, a control terminal receiving a first gate signal of the plurality of gate signals, and a second terminal;
a second transistor, having a first terminal receiving a system high voltage, a control terminal coupled to the second terminal of the first transistor, and a second terminal;
a third transistor, having a first terminal coupled to the second terminal of the second transistor, a control terminal receiving a corresponding one of the plurality of light-emitting signals, and a second terminal coupled to the anode of the LED; and
a first capacitance, coupled between the control terminal of the second transistor and the second terminal of the second transistor.
10 . The tiled display panel according to claim 1 , wherein each of the plurality of LED pixels includes:
an LED, having an anode and a cathode receiving a system low voltage;
a fourth transistor, having a first terminal receiving a pixel data voltage, a control terminal receiving a first gate signal of the plurality of gate signals, and a second terminal;
a fifth transistor, having a first terminal, a control terminal coupled to the second terminal of the fourth transistor, and a second terminal;
a second capacitance, coupled between the first terminal of the fifth transistor and the control terminal of the fifth transistor;
a sixth transistor, having a first terminal receiving a reference voltage, a control terminal receiving the first gate signal, and a second terminal coupled to the first terminal of the fifth transistor;
a seventh transistor, having a first terminal receiving a system high voltage, a control terminal receiving a corresponding one of the plurality of light-emitting signals, and a second terminal coupled to the first terminal of the fifth transistor; and
an eighth transistor, having a first terminal coupled to the second terminal of the fifth transistor, a control terminal receiving a corresponding one of the plurality of light-emitting signals, and a second terminal coupled to the anode of the LED.
11 . The tiled display panel according to claim 1 , wherein each of the plurality of light-emitting circuits comprises:
a ninth transistor, having a first terminal receiving a gate high voltage, a control terminal receiving a second gate signal of the plurality of gate signals, and a second terminal coupled to a corresponding one of the plurality of light-emitting signals; and
a tenth transistor, having a first terminal coupled to the second terminal of the ninth transistor, a control terminal receiving a third gate signal of the plurality of gate signals, and a second terminal receiving a gate low level.
12 . The tiled display panel according to claim 11 , wherein each of the plurality of light-emitting circuits further comprises:
an eleventh transistor, having a first terminal receiving one of a plurality of clock signals, a control terminal coupled to the second terminal of the ninth transistor, and a control terminal coupled to the corresponding one of the plurality of light-emitting signals.
13 . The tiled display panel according to claim 11 , wherein each of the plurality of light-emitting circuits comprises:
a third capacitance, coupled between the second terminal of the ninth transistor and one of a reference voltage and the gate low level.
14 . The tiled display panel according to claim 11 , wherein each of the plurality of light-emitting circuits comprises:
a twelfth transistor, having a first terminal coupled to the second terminal of the ninth transistor, a control terminal receiving a fourth gate signal of the plurality of gate signals, and a second terminal receiving the gate low level.
15 . The tiled display panel according to claim 1 , further comprising:
a plurality of clock lines, receiving a plurality of clock signals and electrically connected to the plurality of light-emitting circuits to transmit the plurality of clock signals to the plurality of light-emitting circuits respectively.
16 . The tiled display panel according to claim 1 , wherein a material of the plurality of substrates comprises one of a P-type amorphous silicon (a-Si) substrate, an N-type amorphous silicon (a-Si) substrate, an indium gallium zinc oxide (IGZO) substrate, and a low-temperature polycrystalline silicon (LTPS) substrate.
17 . The tiled display panel according to claim 1 , wherein the plurality of LED pixels comprise a plurality of red LED pixels, a plurality of green LED pixels, and a plurality of blue LED pixels.