Pixel, method of fabricating the pixel, and electronic device
A pixel may include a first bottom conductive layer including a plurality of first bottom conductive patterns, a second bottom conductive layer disposed on the first bottom conductive layer, and including a plurality of second bottom conductive patterns, and a semiconductor layer disposed on the second bottom conductive layer. The first bottom conductive layer may have a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other. The second bottom conductive layer may have a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other. A thickness of the alloy layer in the first bottom conductive layer may be greater than a thickness of the alloy layer in the second bottom conductive layer.
1 . A pixel, comprising:
a first bottom conductive layer including a plurality of first bottom conductive patterns;
a second bottom conductive layer disposed on the first bottom conductive layer, and including a plurality of second bottom conductive patterns; and
a semiconductor layer disposed on the second bottom conductive layer, wherein
the first bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other,
the second bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other, and
a thickness of the alloy layer in the first bottom conductive layer is greater than a thickness of the alloy layer in the second bottom conductive layer.
2 . The pixel according to claim 1 , wherein
the alloy layer of the first bottom conductive layer includes an alloy of a first metal material included in the first metal layer of the first bottom conductive layer and a second metal material included in the second metal layer of the first bottom conductive layer, and
the alloy layer of the second bottom conductive layer includes an alloy of a first metal material included in the first metal layer of the second bottom conductive layer and a second metal material included in the second metal layer of the second bottom conductive layer.
3 . The pixel according to claim 2 , wherein
the first metal material of the first bottom conductive layer includes aluminum (Al),
the first metal material of the second bottom conductive layer includes Al,
the second metal material of the first bottom conductive layer includes titanium (Ti), and
the second metal material of the second bottom conductive layer includes Ti.
4 . The pixel according to claim 1 , further comprising:
a gate conductive layer disposed on the semiconductor layer, and including a plurality of gate conductive patterns; and
a first source-drain (SD) conductive layer disposed on the gate conductive layer, and including a plurality of first source-drain (SD) conductive patterns.
5 . The pixel according to claim 4 , wherein
the gate conductive layer has a stacked structure including a third metal layer and a fourth metal layer stacked on each other, and
the first SD conductive layer has a stacked structure including a third metal layer and a fourth metal layer stacked on each other.
6 . The pixel according to claim 5 , wherein
the third metal layer of the gate conductive layer and the fourth metal layer of the gate conductive layer directly contact each other, and
the third metal layer of the first SD conductive layer and the fourth metal layer of the first SD conductive layer directly contact each other.
7 . The pixel according to claim 5 , wherein a thickness of at least one of the fourth metal layer of the gate conductive layer and the fourth metal layer of the first SD conductive layer is greater than a thickness of at least one of the second metal layer of the first bottom conductive layer and the second metal layer of the second bottom conductive layer.
8 . The pixel according to claim 1 , further comprising:
a driving transistor connected between a first power voltage line and a second power voltage line, and including an upper gate electrode and a lower gate electrode; and
a light emitting element connected between the driving transistor and the second power voltage line.
9 . The pixel according to claim 8 , wherein the lower gate electrode of the driving transistor includes at least one of the plurality of second bottom conductive patterns.
10 . The pixel according to claim 8 , further comprising:
a hold capacitor connected between the lower gate electrode of the driving transistor and the first power voltage line.
11 . The pixel according to claim 10 , wherein
a first terminal of the hold capacitor includes at least a portion of the lower gate electrode of the driving transistor, and
a second terminal of the hold capacitor includes at least one of the plurality of first bottom conductive patterns.
12 . A method of fabricating a pixel, comprising:
forming a first bottom conductive layer including a plurality of first bottom conductive patterns;
forming a second bottom conductive layer including a plurality of second bottom conductive patterns on the first bottom conductive layer; and
forming a semiconductor layer on the second bottom conductive layer, wherein
the first bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other,
the second bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other, and
a thickness of the alloy layer in the first bottom conductive layer is greater than a thickness of the alloy layer in the second bottom conductive layer.
13 . The method according to claim 12 , further comprising:
forming an insulating layer covering the first bottom conductive layer after forming the first bottom conductive layer.
14 . The method according to claim 13 , wherein forming the insulating layer further comprises heat-treating the insulating layer.
15 . The method according to claim 12 , further comprising:
forming a buffer layer covering the second bottom conductive layer after forming the second bottom conductive layer.
16 . The method according to claim 15 , wherein forming the buffer layer further comprises heat-treating the buffer layer.
17 . The method according to claim 12 , further comprising:
forming a gate insulating layer covering at least a portion of the semiconductor layer after forming the semiconductor layer.
18 . The method according to claim 17 , wherein forming the gate insulating layer further comprises heat-treating the gate insulating layer.
19 . The method according to claim 12 , wherein
the alloy layer of the first bottom conductive layer includes an alloy of a first metal material included in the first metal layer of the first bottom conductive layer and a second metal material included in the second metal layer of the first bottom conductive layer, and
the alloy layer of the second bottom conductive layer includes an alloy of a first metal material included in the first metal layer of the second bottom conductive layer and a second metal material included in the second metal layer of the second bottom conductive layer.
20 . The method according to claim 19 , wherein
the first metal material of the first bottom conductive layer includes aluminum (Al),
the first metal material of the second bottom conductive layer includes Al,
the second metal material of the first bottom conductive layer includes titanium (Ti), and
the second metal material of the second bottom conductive layer includes Ti.
21 . An electronic device, comprising:
a processor to provide input image data; and
a display device to display an image based on the input image data, the display device including a pixel, wherein
the pixel includes:
a first bottom conductive layer including a plurality of first bottom conductive patterns;
a second bottom conductive layer disposed on the first bottom conductive layer, and including a plurality of second bottom conductive patterns; and
a semiconductor layer disposed on the second bottom conductive layer, wherein
the first bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other,
the second bottom conductive layer has a stacked structure including a first metal layer, an alloy layer, and a second metal layer stacked on each other, and
a thickness of the alloy layer in the first bottom conductive layer is greater than a thickness of the alloy layer in the second bottom conductive layer.