IP Library Granted Patent US 12670853
Granted Patent B2
US 12670853 · App. 18/554,998 · Granted Jun 30, 2026

Pixel circuit, driving method therefor, display substrate and display device

Inventors: Wenhui Gao (Beijing, CN); Yonglin Guo (Beijing, CN); Tiaomei Zhang (Beijing, CN); Jingwen Zhang (Beijing, CN); Zhiliang Jiang (Beijing, CN)
Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd.
G09G3/3233G09G2300/0426G09G2300/0819G09G2300/0852G09G2300/0861G09G2310/08G09G2340/0435
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Quick Facts
Patent No.
US 12670853
App. No.
18/554,998
Granted
Jun 30, 2026
Kind
B2
Abstract

A pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, and a first control sub-circuit. The data writing sub-circuit is configured to write a data signal provided by a data line into a second node under control of a first scan line. The compensation sub-circuit is configured to write a threshold voltage of the driving sub-circuit into the first node under control of a second scan line. A period of time for which the data writing sub-circuit writes the data signal into the second node is shorter than a period of time for which the compensation sub-circuit writes the threshold voltage of the driving sub-circuit into the first node.

Claims (23)

1 . A pixel circuit comprising: a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit, a first control sub-circuit, and a voltage stabilizing sub-circuit;

the driving sub-circuit is coupled with a first power supply line, a first node and a third node, and is configured to provide a driving signal to the third node under control of the first node;

the storage sub-circuit is coupled with the first node and a second node;

the data writing sub-circuit is coupled with a data line, a first scan line and the second node, and is configured to write a data signal provided by the data line into the first node through the storage sub-circuit under control of the first scan line;

the compensation sub-circuit is coupled with a second scan line, the first node, and a third node, and is configured to turn on between the first node and the third node under control of the second scan line to write a threshold voltage of the driving sub-circuit into the first node;

the voltage stabilizing sub-circuit is coupled with the first node and a fifth node; and

the first control sub-circuit is coupled with a first control line, a reference voltage line and the fifth node, and is configured to provide a reference voltage signal provided by the reference voltage line to the fifth node under control of the first control line after the data signal is written into the first node;

further comprising: a second control sub-circuit, wherein the second control sub-circuit is coupled with a second control line, the third node and a fourth node, and is configured to transmit the driving signal to the fourth node under control of the second control line, and the fourth node is coupled with a light emitting element;

the pixel circuit further comprises: a first reset sub-circuit, wherein the first reset sub-circuit is coupled with a first reset control line, a first initial signal line and the third node, and is configured to transmit a first initial signal provided by the first initial signal line to the third node under control of the first reset control line; and

a second reset sub-circuit, wherein the second reset sub-circuit is coupled with a second reset control line, a second initial signal line and the fourth node, and is configured to transmit a second initial signal provided by the second initial signal line to the fourth node under control of the second reset control line.

2 . The pixel circuit according to claim 1 , wherein the driving sub-circuit comprises: a driving transistor; a gate of the driving transistor is coupled with the first node, a first electrode of the driving transistor is coupled with the first power supply line, and a second electrode of the driving transistor is coupled with the third node;

the data writing sub-circuit comprises a data writing transistor, wherein a gate of the data writing transistor is coupled with the first scan line, a first electrode of the data writing transistor is coupled with the data line, and a second electrode of the data writing transistor is coupled with the second node;

the compensation sub-circuit comprises a compensation transistor, wherein a gate of the compensation transistor is coupled with the second scan line, a first electrode of the compensation transistor is coupled with the first node, and a second electrode of the compensation transistor is coupled with the third node;

the storage sub-circuit comprises a storage capacitor, wherein a first plate of the storage capacitor is coupled with the first node, and a second plate of the storage capacitor is coupled with the second node;

the voltage stabilizing sub-circuit comprises a voltage stabilizing capacitor, wherein a first plate of the voltage stabilizing capacitor is coupled with the first node, and a second plate of the voltage stabilizing capacitor is coupled with the fifth node;

the first control sub-circuit comprises a first control transistor, wherein a gate of first control transistor is coupled with the first control line, a first electrode of first control transistor is coupled with the reference voltage line, and a second electrode of first control transistor is coupled with the fifth node;

the second control sub-circuit comprises a second control transistor, wherein a gate of the second control transistor is coupled with the second control line, a first electrode of the second control transistor is coupled with the third node, and a second electrode of the second control transistor is coupled with the fourth node;

the first reset sub-circuit comprises a first reset transistor, wherein a gate of the first reset transistor is coupled with the first reset control line, a first electrode of the first reset transistor is coupled with the first initial signal line, and a second electrode of the first reset transistor is coupled with the third node; and

the second reset sub-circuit comprises a second reset transistor, wherein a gate of the second reset transistor is coupled with the second reset control line, a first electrode of the second reset transistor is coupled with the second initial signal line, and a second electrode of the second reset transistor is coupled with the fourth node.

3 . A method for driving a pixel circuit, applied to the pixel circuit according to claim 1 , the method comprising:

the data writing sub-circuit writing the data signal provided by the data line into the first node through the storage sub-circuit under control of the first scan line; the compensation sub-circuit turning on between the first node and the third node under control of the second scan line so that the threshold voltage of the driving sub-circuit is written into the first node; and

the first control sub-circuit providing the reference voltage signal provided by the reference voltage line to the fifth node under control of the first control line, and a potential of the first node is maintained by the voltage stabilizing sub-circuit.

4 . The method according to claim 3 , further comprising: a first reset control line transmitting a first initial signal provided by a first initial signal line to the third node under control of the first reset control line before and after the compensation sub-circuit writes the threshold voltage of the driving sub-circuit into the first node.