Display device with dual driving transistors for brightness range control

1 . A display device, comprising:

at least one pixel circuit, comprising:

a first driving transistor electrically connected to a first voltage terminal;

a second driving transistor electrically connected to the first voltage terminal; and

a light emitting diode having a first terminal and a second terminal, wherein the first terminal is electrically connected to the first driving transistor and the second driving transistor, and the second terminal is electrically connected to a second voltage terminal, and

wherein when the at least one pixel circuit presents a first brightness, the light emitting diode obtains a first current through the first driving transistor, when the at least one pixel circuit presenting a second brightness, the light emitting diode obtains a second current through the second driving transistor, the first brightness is higher than the second brightness, and a current value of the first current is higher than a current value of the second current,

when the at least one pixel circuit presents the first brightness, the first driving transistor receives a data signal according to a first scan signal and generates the first current according to the data signal, and

when the at least one pixel circuit presents the second brightness, the second driving transistor receives the data signal according to a second scan signal and generates the second current according to the data signal.

2 . The display device as claimed in claim 1 , wherein a material of a semiconductor layer in the first driving transistor is different from a material of a semiconductor layer in the second driving transistor.

3 . The display device as claimed in claim 1 , wherein a channel width-to-length ratio in the first driving transistor is higher than a channel width-to-length ratio in the second driving transistor.

4 . The display device as claimed in claim 1 , further comprising:

a logic circuit electrically connected to the at least one pixel circuit, and configured to generate the first scan signal and the second scan signal according to a scan enable signal, a scan signal, and an inverted scan signal.

5 . The display device as claimed in claim 1 , wherein when the at least one pixel circuit presents the first brightness, the light emitting diode obtains a third current through the second driving transistor.

6 . The display device as claimed in claim 5 , wherein the first current is higher than the third current.

7 . The display device as claimed in claim 5 , wherein when the at least one pixel circuit presents the second brightness, the light emitting diode obtains a fourth current through the first driving transistor.

8 . The display device as claimed in claim 7 , wherein the fourth current is lower than the second current.

9 . The display device as claimed in claim 1 , wherein

when the at least one pixel circuit presents the first brightness, the first driving transistor is turned on according to a first control signal during a reset period, and

when the at least one pixel circuit presents the second brightness, the second driving transistor is turned on according to a second control signal during the reset period.

10 . The display device as claimed in claim 9 , wherein the at least one pixel circuit further comprises:

a control signal generation circuit configured to generate the first control signal and the second control signal according to a reference signal and at least one reference voltage.

11 . The display device as claimed in claim 1 , wherein

the first driving transistor has a first bottom gate terminal,

the second driving transistor has a second bottom gate terminal, and

a bias voltage at the first bottom gate terminal is different from a bias voltage at the second bottom gate terminal.

12 . The display device as claimed in claim 1 , wherein the at least one pixel circuit further comprises:

a first scan transistor, wherein a first terminal of the first scan transistor receives the data signal, a second terminal of the first scan transistor is electrically connected to a first terminal of the first driving transistor and a first terminal of the second driving transistor, and a control terminal of the first scan transistor receives the first scan signal; and

a second scan transistor, wherein a first terminal of the second scan transistor receives the data signal, a second terminal of the second scan transistor is electrically connected to the first terminal of the first driving transistor and the first terminal of the second driving transistor, and a control terminal of the second scan transistor receives the second scan signal.

13 . The display device as claimed in claim 1 , wherein the at least one pixel circuit further comprises:

a first scan transistor, wherein a first terminal of the first scan transistor receives a first data signal, a second terminal of the first scan transistor is electrically connected to a first terminal of the first driving transistor, and a control terminal of the first scan transistor receives a scan signal; and

a second scan transistor, wherein a first terminal of the second scan transistor receives a second data signal, a second terminal of the second scan transistor is electrically connected to a first terminal of the second driving transistor, and a control terminal of the second scan transistor receives the scan signal.

14 . The display device as claimed in claim 1 , wherein the at least one pixel circuit further comprises:

a scan transistor, wherein a first terminal of the scan transistor receives a data signal, a second terminal of the scan transistor is electrically connected to a first terminal of the first driving transistor and a first terminal of the second driving transistor, and a control terminal of the scan transistor receives a scan signal.

15 . A display device, comprising:

at least one pixel circuit, comprising:

a first driving transistor electrically connected to a first voltage terminal;

a second driving transistor electrically connected to the first voltage terminal; and

a first light emitting diode having a first terminal and a second terminal, wherein the first terminal of the first light emitting diode is electrically connected to the first driving transistor, and the second terminal of the first light emitting diode is electrically connected to a second voltage terminal; and

a second light emitting diode having a first terminal and a second terminal, wherein the first terminal of the second light emitting diode is electrically connected to the second driving transistor, and the second terminal of the second light emitting diode is electrically connected to the second voltage terminal,

wherein when the at least one pixel circuit presents a first brightness, the first light emitting diode obtains a first current through the first driving transistor, when the at least one pixel circuit presenting a second brightness, the second light emitting diode obtains a second current through the second driving transistor, the first brightness is higher than the second brightness, and a current value of the first current is higher than a current value of the second current, and

wherein a second current density required for the second light emitting diode to achieve an optimal external quantum efficiency of the second light emitting diode is lower than a first current density required for the first light emitting diode to achieve an optimal external quantum efficiency of the first light emitting diode.

16 . The display device as claimed in claim 15 , wherein a material of the semiconductor layer in the first driving transistor is different from a material of the semiconductor layer in the second driving transistor.

17 . The display device as claimed in claim 15 , wherein a channel width-to-length ratio in the first driving transistor is higher than a channel width-to-length ratio in the second driving transistor.

18 . The display device as claimed in claim 15 , wherein

the first driving transistor has a first bottom gate terminal,

the second driving transistor has a second bottom gate terminal, and

a bias voltage at the first bottom gate terminal is different from a bias voltage at the second bottom gate terminal.