Display device

1 . A display device comprising:

a first pixel coupled to a control line; and

a control stage configured to selectively couple the control line to a first supply voltage line or a second supply voltage line,

wherein the control stage comprises:

a first transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the control line, and a gate electrode coupled to a first node;

a second transistor including a first electrode coupled to the control line, a second electrode coupled to the second supply voltage line, and a gate electrode coupled to a second node; and

a third transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode, and a sub-gate electrode, and

wherein the main gate electrode and the sub-gate electrode of the third transistor are electrically coupled to the gate electrode of the second transistor.

2 . The display device according to claim 1 ,

wherein a voltage applied to the first supply voltage line is higher than a voltage applied to the second supply voltage line.

3 . The display device according to claim 1 ,

wherein the sub-gate electrode of the third transistor is coupled to the main gate electrode of the third transistor.

4 . The display device according to claim 1 ,

wherein the main gate electrode of the third transistor is disposed over an active layer, and

wherein the sub-gate electrode of the third transistor is disposed under the active layer.

5 . The display device according to claim 1 ,

wherein the first transistor, the second transistor, and the third transistor are all P-type transistors.

6 . The display device according to claim 1 ,

wherein the first transistor, the second transistor, and the third transistor are all N-type transistors.

7 . The display device according to claim 1 ,

wherein at least one of the first transistor, the second transistor, and the third transistor is a P-type transistor, and

wherein at least another one of the first transistor, the second transistor, and the third transistor is an N-type transistor.

8 . The display device according to claim 1 ,

wherein each of the first transistor, the second transistor, and the third transistor includes an active layer including a poly silicon.

9 . The display device according to claim 1 ,

wherein each of the first transistor, the second transistor, and the third transistor includes an active layer including an oxide semiconductor.

10 . The display device according to claim 1 ,

wherein at least one of the first transistor, the second transistor, and the third transistor includes an active layer including a poly silicon, and

wherein at least another one of the first transistor, the second transistor, and the third transistor includes an active layer including an oxide semiconductor.

11 . The display device according to claim 1 ,

wherein the control stage further comprises:

a fourth transistor including a first electrode electrically coupled to the gate electrode of the second transistor, a second electrode coupled to a control start line or a previous control line, and a gate electrode coupled to a first clock line.

12 . The display device according to claim 11 ,

wherein the control stage further comprises:

a fifth transistor including a first electrode electrically coupled to the gate electrode of the first transistor, a second electrode coupled to a second clock line, and a gate electrode; and

a first capacitor coupled between the gate electrode of the fifth transistor and the first electrode of the fifth transistor.

13 . A display device comprising:

a first pixel coupled to a control line; and

a control stage configured to selectively couple the control line to a first supply voltage line or a second supply voltage line,

wherein the control stage comprises:

a first transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the control line, and a gate electrode coupled to a first node;

a second transistor including a first electrode coupled to the control line, a second electrode coupled to the second supply voltage line, and a gate electrode coupled to a second node; and

a third transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode, and a sub-gate electrode, and

wherein the sub-gate electrode of the third transistor is coupled to a node different from a node to which the main gate electrode of the third transistor is connected, and

the sub-gate electrode of the third transistor is coupled to the first supply voltage line.

14 . The display device according to claim 13 ,

wherein the main gate electrode of the third transistor is disposed over an active layer, and

wherein the sub-gate electrode of the third transistor is disposed under the active layer.

15 . The display device according to claim 13 ,

wherein the first transistor, the second transistor, and the third transistor are all P-type transistors.

16 . The display device according to claim 13 ,

wherein the first transistor, the second transistor, and the third transistor are all N-type transistors.

17 . The display device according to claim 13 ,

wherein at least one of the first transistor, the second transistor, and the third transistor is a P-type transistor, and

wherein at least another one of the first transistor, the second transistor, and the third transistor is an N-type transistor.

18 . The display device according to claim 13 ,

wherein each of the first transistor, the second transistor, and the third transistor includes an active layer including a poly silicon.

19 . The display device according to claim 13 ,

wherein each of the first transistor, the second transistor, and the third transistor includes an active layer including an oxide semiconductor.

20 . The display device according to claim 13 ,

wherein at least one of the first transistor, the second transistor, and the third transistor includes an active layer including a poly silicon, and

wherein at least another one of the first transistor, the second transistor, and the third transistor includes an active layer including an oxide semiconductor.

21 . A display device comprising:

a first pixel coupled to a control line; and

a control stage configured to selectively couple the control line to a first supply voltage line or a second supply voltage line,

wherein the control stage comprises:

a first transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the control line, and a gate electrode coupled to a first node;

a second transistor including a first electrode coupled to the control line, a second electrode coupled to the second supply voltage line, and a gate electrode coupled to a second node; and

a third transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode, and a sub-gate electrode,

wherein the sub-gate electrode of the third transistor is coupled to a node different from a node to which the main gate electrode of the third transistor is connected,

wherein the control stage further comprises:

a fourth transistor including a first electrode electrically coupled to the gate electrode of the second transistor, a second electrode coupled to a control start line or a previous control line, and a gate electrode coupled to a first clock line.

22 . The display device according to claim 21 ,

wherein the control stage further comprises:

a fifth transistor including a first electrode electrically coupled to the gate electrode of the first transistor, a second electrode coupled to a second clock line, and a gate electrode; and

a first capacitor coupled between the gate electrode of the fifth transistor and the first electrode of the fifth transistor.