Gate driving circuit and display device including the same

1 . A gate driving circuit comprising:

at least one stage circuit configured to supply gate signals to a plurality of gate lines and including a first node, wherein the at least one stage circuit includes:

N output buffer circuits configured to sequentially output pulses of the gate signals in response to pulses of corresponding clock signals while the first node is in a pre-charged state; and

an output improvement circuit configured to improve an output deviation of a first output buffer circuit among the N output buffer circuits that outputs a first gate signal among the sequentially output pulses of the gate signals and improve an output deviation of an Nth output buffer circuit among the N output buffer circuits that outputs a last gate signal among the sequentially output pulses of the gate signals, among the N output buffer circuits,

wherein the output improvement circuit includes a first output improvement circuit configured to reinforce a voltage of the first node in response to a previous clock signal whose phase is one phase earlier than that of a clock signal input to the first output buffer circuit, and

wherein N is a natural number greater than or equal to 2.

2 . The gate driving circuit of claim 1 , wherein the output improvement circuit includes:

a second output improvement circuit configured to attenuate the voltage of the first node in response to a next clock signal whose phase is one phase later than that of the clock signal input to the Nth output buffer circuit.

3 . The gate driving circuit of claim 2 , wherein the first output improvement circuit reinforces the voltage of the first node by a rising edge of the previous clock signal before the first output buffer circuit outputs the first gate signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the next clock signal after the Nth output buffer circuit outputs the first gate signal.

4 . The gate driving circuit of claim 2 , wherein the first output improvement circuit includes a first transistor comprising a gate terminal to which the voltage of the first node is input, a first terminal to which the previous clock signal is input, and a second terminal from which the previous clock signal is output, and a first capacitor connected to the gate terminal and the second terminal to reinforce the voltage of the first node.

5 . The gate driving circuit of claim 2 , wherein the second output improvement circuit includes a second transistor including a gate terminal to which the voltage of the first node is applied, a first terminal to which the next clock signal is input, and a second terminal from which the next clock signal is output, and a second capacitor connected to the gate terminal and the second terminal to attenuate the voltage of the first node.

6 . The gate driving circuit of claim 2 , wherein the first output improvement circuit includes a first capacitor having one end connected to the first node and another end connected to a clock line to which the previous clock signal is input.

7 . The gate driving circuit of claim 2 , wherein the second output improvement circuit includes a second capacitor having one end connected to the first node and another end connected to a clock line to which the next clock signal is input.

8 . The gate driving circuit of claim 2 , wherein when a length of a high voltage level of the clock signal corresponds to M horizontal periods, the stage circuit includes M−1 first output improvement circuits and M−1 second output improvement circuits, and wherein M is a natural number greater than or equal to 2.

9 . A gate driving circuit comprising:

a first stage circuit, a second stage circuit, and a third stage circuit configured to supply gate signals to a plurality of gate lines and including a first node,

wherein each of the first stage circuit, the second stage circuit, and the third stage circuit includes:

first to Nth output buffer circuits configured to sequentially output pulses of gate signals in response to pulses of corresponding clock signals while the first node is in a pre-charged state; and

an output improvement circuit configured to improve an output deviation of the first output buffer circuit that outputs a first gate signal among the sequentially output pulses of the gate signals and an output deviation of the Nth output buffer circuit that outputs a last gate signal among the sequentially output pulses of the gate signals,

wherein the output improvement circuit of the second stage circuit includes a first output improvement circuit configured to reinforce a voltage of the first node in response to a first stage gate signal, which is a gate signal output from the Nth output buffer circuit of the first stage circuit, and

wherein N is a natural number greater than or equal to 2.

10 . The gate driving circuit of claim 9 , wherein the output improvement circuit of the second stage circuit includes:

a second output improvement circuit configured to attenuate the voltage of the first node in response to a second stage gate signal, which is a gate signal output from a first output buffer circuit of the third stage circuit.

11 . The gate driving circuit of claim 10 , wherein the first output improvement circuit reinforces the voltage of the first node by a rising edge of the first stage gate signal before the first output buffer circuit outputs a gate signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the second stage gate signal after the Nth output buffer circuit outputs a gate signal.

12 . The gate driving circuit of claim 10 , wherein the first output improvement circuit includes a first transistor including a gate terminal to which the voltage of the first node is applied, a first terminal to which the first stage gate signal is input, and a second terminal from which the first stage gate signal is output, and a first capacitor connected to the gate terminal and the second terminal to reinforce the voltage of the first node.

13 . The gate driving circuit of claim 10 , wherein the second output improvement circuit includes a second transistor including a gate terminal to which the voltage of the first node is applied, a first terminal to which the second stage gate signal is input, and a second terminal from which the second stage gate signal is output, and a second capacitor connected to the gate terminal and the second terminal to attenuate the voltage of the first node.

14 . The gate driving circuit of claim 10 , wherein the first output improvement circuit includes a first capacitor having one end connected to the first node and another end connected to a signal line to which the first stage gate signal is input.

15 . The gate driving circuit of claim 10 , wherein the second output improvement circuit includes a second capacitor having one end connected to the first node and another end connected to a signal line to which the second stage gate signal is input.

16 . A display device comprising:

a display panel that includes a plurality of pixel circuits, wherein the plurality of pixel circuits are connected to corresponding data lines and gate lines;

a data driving circuit configured to output a data signal applied to a data line from the data lines;

a gate driving circuit configured to receive a clock signal and supply a gate signal to a gate line from the gate lines; and

a timing controller configured to control driving of the data driving circuit and the gate driving circuit and,

wherein the gate driving circuit is configured to:

supply gate signals to the gate lines, and includes a first stage circuit, a second stage circuit, and a third stage circuit including a first node,

each of the first stage circuit, the second stage circuit, and the third stage circuit includes:

first to Nth output buffer circuits configured to sequentially output pulses of the gate signal using pulses of the corresponding clock signal while the first node is in a pre-charged state; and

an output improvement circuit configured to improve an output deviation of the first output buffer circuit that outputs a first gate signal among the sequentially output pulses of the gate signals and an output deviation of the Nth output buffer circuit that outputs a first stage gate signal among the sequentially output pulses of the gate signals,

wherein the output improvement circuit of the second stage circuit includes a first output improvement circuit configured to reinforce a voltage of the first node in response to the first stage gate signal, which is a gate signal output from the Nth output buffer circuit of the first stage circuit, and

wherein N is a natural number greater than or equal to 2.

17 . The display device of claim 16 , wherein the output improvement circuit of the second stage circuit includes:

a second output improvement circuit configured to attenuate the voltage of the first node after the gate signal is output from the Nth output buffer circuit.

18 . The display device of claim 17 , wherein the first output improvement circuit reinforces the voltage of the first node in response to a pulse of a previous clock signal whose phase is earlier than that of a clock signal input to the first output buffer circuit, and the second output improvement circuit attenuates the voltage of the first node in response to a pulse of a next clock signal whose phase is later than a clock signal input to the Nth output buffer circuit.

19 . The display device of claim 18 , wherein the first output improvement circuit reinforces the voltage of the first node by a rising edge of the previous clock signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the next clock signal.

20 . The display device of claim 17 , wherein the first output improvement circuit reinforces the voltage of the first node in response to a pulse of the first stage gate signal, which is a gate signal output from a last output buffer circuit of the first stage circuit, and the second output improvement circuit attenuates the voltage of the first node in response to a pulse of a second stage gate signal, which is a gate signal output from a first output buffer circuit of the third stage circuit.

21 . The display device of claim 20 , wherein the first output improvement circuit reinforces the voltage of the first node by a rising edge of the first stage gate signal, and the second output improvement circuit attenuates the voltage of the first node by a falling edge of the second stage gate signal.