Switch circuit, display driving circuit, display system, and circuit operation method thereof
A switch circuit includes a first switch, a second switch, and a third switch, where each switch has a first terminal, a second terminal, and a control terminal. The switch circuit has four signal terminals and three control terminals, where a first signal terminal is coupled to a first terminal of the first switch. A second signal terminal is coupled to a second terminal of the first switch and a first terminal of the second switch. The third signal terminal is coupled to a first terminal of the third switch. The fourth signal terminal is coupled to a second terminal of the second switch and a second terminal of the third switch. The three control terminals of the switch circuit are respectively coupled to control terminals of the three switches, for receiving corresponding control signals.
1 . A display driving circuit comprising:
a plurality of pins, wherein each pin is a hardware interface between internal and external of the display driving circuit, the plurality of pins comprising a first pin to an nth pin and at least one source driving pin;
a power generator comprising a first output terminal to an nth output terminal, configured to respectively provide a first source driving voltage to an nth source driving voltage;
a source driver comprising a first input terminal to an nth input terminal, respectively coupled to the first output terminal to the nth output terminal of the power generator, and at least one output terminal, the at least one output terminal respectively coupled to the at least one source driving pin, configured to output at least one source driving signal; and
a first switch circuit comprising a first signal terminal, a second signal terminal, a third signal terminal, and a fourth signal terminal, wherein one of the first signal terminal and the second signal terminal is coupled to the first output terminal of the power generator, and the other one of the first signal terminal and the second signal terminal is coupled to the first pin;
wherein n is an integer greater than or equal to 1.
2 . The display driving circuit of claim 1 , wherein the first switch circuit further comprises:
a first switch comprising a first terminal, a second terminal, and a control terminal;
a second switch comprising a first terminal, a second terminal, and a control terminal;
a third switch comprising a first terminal, a second terminal, and a control terminal;
a first control terminal coupled to the control terminal of the first switch, configured to receive a first control signal, the first control signal configured to turn on or turn off the first switch;
a second control terminal coupled to the control terminal of the second switch, configured to receive a second control signal, the second control signal configured to turn on or turn off the second switch; and
a third control terminal coupled to the control terminal of the third switch, configured to receive a third control signal, the third control signal configured to turn on or turn off the third switch;
wherein the first signal terminal is coupled to the first terminal of the first switch;
the second signal terminal is coupled to the second terminal of the first switch and the first terminal of the second switch;
the third signal terminal is coupled to the first terminal of the third switch; and
the fourth signal terminal is coupled to the second terminal of the second switch and the second terminal of the third switch.
3 . A circuit operation method configured to control the display driving circuit of claim 2 , the circuit operation method comprising:
in a third mode, the first switch is turned on, the second switch is turned off, the third switch is turned on, a third signal path is formed between the third signal terminal and the fourth signal terminal through the third switch, and a fourth signal path is formed between the first signal terminal and the second signal terminal through the first switch.
4 . The circuit operation method of claim 3 , further comprising:
in a first mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and a first signal path is formed between the second signal terminal and the fourth signal terminal through the second switch.
5 . The circuit operation method of claim 4 , further comprising:
in a second mode, the first switch is turned on, the second switch is turned on, the third switch is turned off, and a second signal path is formed between the first signal terminal and the fourth signal terminal through the first switch and the second switch;
in a fourth mode, the first switch is turned off, the second switch is turned off, the third switch is turned on, and a fifth signal path is formed between the third signal terminal and the fourth signal terminal through the third switch;
in a fifth mode, the first switch is turned off, the second switch is turned on, the third switch is turned on, a sixth signal path is formed between the third signal terminal and the second signal terminal through the second switch and the third switch, and a seventh signal path is formed between the third signal terminal and the fourth signal terminal through the third switch; and
in a sixth mode, the first switch is turned on, the second switch is turned off, the third switch is turned off, and an eighth signal path is formed between the first signal terminal and the second signal terminal through the first switch.
6 . The circuit operation method of claim 3 , further comprising:
in a second mode, the first switch is turned on, the second switch is turned on, the third switch is turned off, and a second signal path is formed between the first signal terminal and the fourth signal terminal through the first switch and the second switch.
7 . The circuit operation method of claim 6 , further comprising:
in a first mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and a first signal path is formed between the second signal terminal and the fourth signal terminal through the second switch;
in a fourth mode, the first switch is turned off, the second switch is turned off, the third switch is turned on, and a fifth signal path is formed between the third signal terminal and the fourth signal terminal through the third switch;
in a fifth mode, the first switch is turned off, the second switch is turned on, the third switch is turned on, a sixth signal path is formed between the third signal terminal and the second signal terminal through the second switch and the third switch, and a seventh signal path is formed between the third signal terminal and the fourth signal terminal through the third switch; and
in a sixth mode, the first switch is turned on, the second switch is turned off, the third switch is turned off, and an eighth signal path is formed between the first signal terminal and the second signal terminal through the first switch.
8 . A display system comprising:
the display driving circuit of claim 1 , and a display;
wherein the plurality of pins of the display driving circuit further comprises at least one gate driving pin;
the display driving circuit further comprises a gate driver, the gate driver comprising at least one input terminal configured to receive at least one gate driving voltage, and at least one output terminal respectively coupled to the at least one gate driving pin, configured to respectively output at least one gate driving signal; and
the display comprises a plurality of input terminals respectively coupled to the at least one source driving pin and the at least one gate driving pin of the display driving circuit, the display configured to display a display image according to at least the at least one source driving signal and the at least one gate driving signal.
9 . The display system of claim 8 , wherein the display comprises a member selected from a group consisting of an Electrophoretic Display (EPD), a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode display (OLED), a Quantum Dot Light-Emitting Diode display (QLED), a Micro Light-Emitting Diode display (Micro-LED), a Field Emission Display (FED), a Plasma Display Panel (PDP), a Surface-Conduction Electron-Emitter Display (SED), an Electrowetting Display, an Interferometric Modulator Display (IMOD), and an Electrochromic Display.
10 . The display driving circuit of claim 1 , further comprising:
a memory comprising an input terminal coupled to the fourth signal terminal of the first switch circuit, and an output terminal configured to output predetermined data; and
a lookup circuit comprising an input terminal configured to receive the predetermined data, and at least one output terminal configured to output a lookup result;
wherein the source driver further comprises at least one data input terminal coupled to the at least one output terminal of the lookup circuit, and the source driver outputs the at least one source driving signal according to at least the lookup result.
11 . The display driving circuit of claim 1 , wherein the plurality of pins further comprises at least one gate driving pin, and the display driving circuit further comprises:
a gate driver comprising at least one input terminal configured to receive at least one gate driving voltage, and at least one output terminal respectively coupled to the at least one gate driving pin, configured to respectively output at least one gate driving signal.
12 . The display driving circuit of claim 1 , wherein:
the second output terminal to the nth output terminal of the power generator are respectively coupled to the second pin to the nth pin, and the first pin to the nth pin are respectively coupled to a first capacitor to an nth capacitor, and the first capacitor to the nth capacitor are disposed external to the display driving circuit.
13 . The display driving circuit of claim 1 , further comprising:
a second switch circuit comprising a first signal terminal, a second signal terminal, a third signal terminal, and a fourth signal terminal, wherein one of the first signal terminal and the second signal terminal of the second switch circuit is coupled to the second output terminal of the power generator, and the other one of the first signal terminal and the second signal terminal of the second switch circuit is coupled to the second pin.
14 . A switch circuit comprising:
a first switch comprising a first terminal, a second terminal, and a control terminal;
a second switch comprising a first terminal, a second terminal, and a control terminal;
a third switch comprising a first terminal, a second terminal, and a control terminal;
a first signal terminal coupled to the first terminal of the first switch;
a second signal terminal coupled to the second terminal of the first switch and the first terminal of the second switch;
a third signal terminal coupled to the first terminal of the third switch;
a fourth signal terminal coupled to the second terminal of the second switch and the second terminal of the third switch;
a first control terminal coupled to the control terminal of the first switch, configured to receive a first control signal, the first control signal configured to turn on or turn off the first switch;
a second control terminal coupled to the control terminal of the second switch, configured to receive a second control signal, the second control signal configured to turn on or turn off the second switch; and
a third control terminal coupled to the control terminal of the third switch, configured to receive a third control signal, the third control signal configured to turn on or turn off the third switch;
wherein in a first mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and a first signal path is formed between the second signal terminal and the fourth signal terminal through the second switch; and
wherein in a third mode, the first switch is turned on, the second switch is turned off, the third switch is turned on, a third signal path is formed between the third signal terminal and the fourth signal terminal through the third switch, and a fourth signal path is formed between the first signal terminal and the second signal terminal through the first switch.
15 . The switch circuit of claim 14 ,
wherein in a sixth mode, the first switch is turned on, the second switch is turned off, the third switch is turned off, and an eighth signal path is formed between the first signal terminal and the second signal terminal through the first switch.
16 . The switch circuit of claim 15 ,
wherein in a fourth mode, the first switch is turned off, the second switch is turned off, the third switch is turned on, and a fifth signal path is formed between the third signal terminal and the fourth signal terminal through the third switch; and
wherein in a fifth mode, the first switch is turned off, the second switch is turned on, the third switch is turned on, a sixth signal path is formed between the third signal terminal and the second signal terminal through the second switch and the third switch, and a seventh signal path is formed between the third signal terminal and the fourth signal terminal through the third switch.
17 . The switch circuit of claim 14 ,
wherein in a second mode, the first switch is turned on, the second switch is turned on, the third switch is turned off, and a second signal path is formed between the first signal terminal and the fourth signal terminal through the first switch and the second switch.
18 . The switch circuit of claim 14 ,
wherein in a fourth mode, the first switch is turned off, the second switch is turned off, the third switch is turned on, and a fifth signal path is formed between the third signal terminal and the fourth signal terminal through the third switch.
19 . The switch circuit operation of claim 14 ,
wherein in a fifth mode, the first switch is turned off, the second switch is turned on, the third switch is turned on, a sixth signal path is formed between the third signal terminal and the second signal terminal through the second switch and the third switch, and a seventh signal path is formed between the third signal terminal and the fourth signal terminal through the third switch.
20 . The switch circuit of claim 14 , wherein each of the first switch, second switch, and third switch comprises a member selected from a group consisting of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Silicon Controlled Rectifier (SCR), a Gate Turn-Off Thyristor (GTO), a Complementary Metal-Oxide-Semiconductor (CMOS) switch, a Junction Field-Effect Transistor (JFET), a High Electron Mobility Transistor (HEMT), a Static Induction Transistor (SIT), a Two-Dimensional Electron Gas Field-Effect Transistor (2DEG FET), a Silicon Carbide based power device, a Gallium Nitride based power device, and a Micro-Electro-Mechanical Systems (MEMS) switch.