Display panel and display module

1 . A display panel, comprising: a display area and a peripheral area, the display area including a plurality of pixels arranged in an array extending in a first direction and a second direction, each pixel including a plurality of sub-pixels arranged in the first direction, wherein

the peripheral area includes a first signal line arrangement region and a second signal line arrangement region that are arranged around the display area; the first signal line arrangement region includes a plurality of first signal lines extending in a same direction, and the second signal line arrangement region includes a plurality of second signal lines extending in a same direction; the first signal line arrangement region and the second signal line arrangement region are both in a shape of a narrow strip, and include borders that are close to and non-overlapping with each other, and the borders extend in a same direction; the display panel comprises: a plurality of first lead-out lines including a first reference lead-out line, data lines including a first reference data line, a plurality of second lead-out lines, and gate lines;

wherein a border of the first signal line arrangement region proximate to the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions in a one-to-one correspondence, and are electrically connected to the plurality of first signal lines in a one-to-one correspondence; a first lead-out line is electrically connected to a data line; the plurality of first lead-out positions include a first reference lead-out position, and the first reference lead-out line is led out from the first reference lead-out position and electrically connected to the first reference data line; a width of the first signal line arrangement region corresponding to the first reference lead-out position is b0; a width b of the first signal line arrangement region corresponding to at least partially continuously distributed first target lead-out positions except for the first reference lead-out position satisfies:

b 0−[int( kΔ 1/ P 1)]( W data +S data )≤ b≤b 0−[int( kΔ 1/ P 1)−1]( W data +S data );

wherein Δ1 is a distance between a first target lead-out position and the first reference lead-out position in the first direction, P1 is an arrangement period of a pixel in the first direction, k is a number of sub-pixels in the pixel, W data is a width of a first signal line, and S data is a distance between the adjacent first signal lines of the plurality of first signal lines;

a border of the second signal line arrangement region proximate to the display area includes a plurality of second lead-out positions, and the plurality of second lead-out lines are led out from the plurality of second lead-out positions in one-to-one correspondence, and are electrically connected to the plurality of the second signal lines in one-to-one correspondence; a second lead-out line is electrically connected to a gate line; at least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction.

2 . The display panel according to claim 1 , wherein the first direction is perpendicular to the second direction;

an extension direction of at least part of the first signal line arrangement region and an extension direction of at least part of the second signal line arrangement region are each different from both the first direction and the second direction.

3 . The display panel according to claim 1 , wherein for the at least partially continuously distributed first target lead-out positions, a width b1 of the first signal line arrangement region corresponding to a first target lead-out position corresponding to a sub-pixel with a same color as a sub-pixel electrically connected to the first reference data line satisfies:

b 1= b 0−[int( kΔ 1/ P 1)]( W data +S data ).

4 . The display panel according to claim 1 , wherein the at least partially continuously distributed first target lead-out positions include three continuously distributed first target lead-out positions, and the three continuously distributed first target lead-out positions are electrically connected to three sub-pixels of a pixel in a one-to-one correspondence, an overall width of three first lead-out lines corresponding to the three continuously distributed first target lead-out positions is less than or equal to an arrangement period of a sub-pixel in the first direction.

5 . The display panel according to claim 1 , wherein the plurality of second lead-out positions include a second reference lead-out position, the plurality of second lead-out lines includes a second reference lead-out line, the gate lines includes a reference gate line; and the second reference lead-out line is led out from the second reference lead-out position and is electrically connected to the reference gate line; a width of the second signal line arrangement region corresponding to the second reference lead-out position is c0; among at least partially continuously distributed second target lead-out positions except for the second reference lead-out position, a width c of the second signal line arrangement region corresponding to each second target lead-out position satisfies:

c 0−[int( kΔ 2/ P 1)+1]( W gate +S gate )≤ c≤c 0−[int( kΔ 2/ P 1)−1]( W gate +S gate ),

wherein Δ2 is a distance between a second target lead-out position and the second reference lead-out position in the first direction, W gate is a width of a second signal line, and S gate is a distance between adjacent second signal lines of the plurality of signal lines.

6 . The display panel according to claim 5 , wherein a distance between the first reference lead-out position and the second reference lead-out position in the first direction is less than the arrangement period of the pixel in the first direction;

the at least partially continuously distributed second target lead-out positions and the at least partially continuously distributed first target lead-out positions are alternately distributed in the first direction.

7 . The display panel according to claim 6 , characterized wherein among the at least partially continuously distributed first target lead-out positions, m second target lead-out positions are provided on each of two sides of every three first target lead-out positions, where m is one of three values 4, 5, or 6.

8 . The display panel according to claim 7 , wherein the three first target lead-out positions are arranged at equal intervals, and the m second target lead-out positions are arranged at equal intervals; a distance between adjacent first target lead-out positions of the three first target lead-out positions is greater than a distance between adjacent second target lead-out positions of the m second target lead-out positions; and/or

the three first target lead-out positions are arranged at equal intervals, and the m second target lead-out positions are arranged at equal intervals; a width occupied by the three first target lead-out positions in the first direction is less than a width occupied by the m second target lead-out positions in the first direction.

9 . The display panel according to claim 1 , wherein an included angle between a first lead-out line and a first signal line electrically connected thereto is greater than or equal to 90 degrees; an included angle between a second lead-out line and a second signal line electrically connected thereto is greater than or equal to 90 degrees; and/or

a width of the first lead-out line is greater than a width of the first signal line connected thereto; and/or a width of the second lead-out line is greater than a width of the second signal line connected thereto.

10 . The display panel according to claim 1 , wherein the plurality of second lead-out positions include a second reference lead-out position, the plurality of second signal lines includes a second reference signal line, and the gate lines includes a reference gate line; and the second reference signal line is led out from the second reference lead-out position and is electrically connected to the reference gate line; a width of the second signal line arrangement region corresponding to the second reference lead-out position is c0; among at least partially continuously distributed second target lead-out positions except for the second reference lead-out position, a width c of the second signal line arrangement region corresponding to each second target lead-out position satisfies:

c 0−[int(Δ3/ P sub2 )+1]( W gate +S gate )≤ c≤c 0−[int(Δ3/ P sub2 )−1]( W gate +S gate ),

wherein Δ3 is a distance between a second target lead-out position and the second reference lead-out position in the second direction, P sub2 is an arrangement period of a sub-pixel in the second direction, W gate is a width of a second signal line, and S gate is a distance between adjacent second signal lines of the plurality of second signal lines.

11 . The display panel according to claim 10 , wherein the gate lines further include a target gate line; for the at least partially continuously distributed second target lead-out positions, a width c1 of the second signal line arrangement region corresponding to a second lead-out position electrically connected to the target gate line spaced an odd-numbered gate lines from the reference gate line satisfies:

c 1= c 0−[int(Δ3/ P sub2 )]( W gate +S gate ); and/or

the width b satisfies: b=b0−[int(kΔ1/P1)](W gate +S gate ), wherein P1 is the arrangement period of the pixel in the first direction.

12 . The display panel according to claim 1 , wherein the first signal line arrangement region is closer to the display area than the second signal line arrangement region, or the second signal line arrangement region is closer to the display area than the first signal line arrangement region.

13 . The display panel according to claim 12 , wherein in a case where the second signal line arrangement region is closer to the display area than the first signal line arrangement region, and the first lead-out lines are led out in the second direction, an included angle θ1 between a first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and a second signal line that is located in the second signal line arrangement region and is immediately adjacent to the first signal line arrangement region satisfies:

sin θ1=[ I 1( W data +S data )cos α1]/ P 1,

wherein α1 is an included angle between the second signal line that is located in the second signal line arrangement region and is immediately adjacent to the first signal line arrangement region and the first direction, I1 is a number of first target lead-out positions corresponding to a range of the arrangement period of the pixel in the first direction, and P1 is the arrangement period of the pixel in the first direction; or

in a case where the first signal line arrangement region is closer to the display area than the second signal line arrangement region, and the second lead-out lines are led out in the second direction, an included angle θ2 between a first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and a second signal line that is located in the second signal line arrangement region and is immediately adjacent to the first signal line arrangement region satisfies:

sin θ2 =[I 2( W gate +S gate )cos α2 ]/P 1

wherein α2 is an included angle between the first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and the first direction, I2 is a number of second target lead-out positions corresponding to a range of the arrangement period of the pixel in the first direction, and P1 is the arrangement period of the pixel in the first direction; or

in a case where the first signal line arrangement region is closer to the display area than the second signal line arrangement region, and the second lead-out lines are led out in the first direction, an included angle θ3 between a first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and a second signal line that is located in the second signal line arrangement region and is immediately adjacent to the first signal line arrangement region satisfies:

sin θ3=[ I 3( W gate +S gate )sin α3]/ P 2,

wherein α3 is an included angle between the first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and the first direction, I3 is a number of second target lead-out positions corresponding to a range of an arrangement period of a pixel in the second direction, and P2 is the arrangement period of the pixel in the second direction.

14 . The display panel according to claim 12 , wherein

the second signal line arrangement region is closer to the display area than the first signal line arrangement region, and an included angle θ between a first signal line that is located in the first signal line arrangement region and is immediately adjacent to the second signal line arrangement region and a second signal line that is located in the second signal line arrangement region and is immediately adjacent to the first signal line arrangement region is in a range of 1° to 5°, inclusive.

15 . The display panel according to claim 1 , wherein

the display panel comprises a gate driving circuit located in the peripheral area, wherein the gate driving circuit has a plurality of shift register units, at least part of the plurality of shift register units are electrically connected to the gate lines for sending gate driving signals to the gate lines; an overall span of the plurality of shift register units in the second direction is less than an overall span of the pixels in the display area in the second direction.

16 . The display panel according to claim 15 , wherein

the display area includes a column of pixel with a longest span, in a plane where the display panel is located, a first orthographic projection of the plurality of shift register units on a straight line where the column of pixels with the longest span is located is within a second orthographic projection of the column of pixels with the longest span on the straight line where the column of pixels with the longest span is located.

17 . The display panel according to claim 16 , wherein

the plurality of shift register units are located on two sides of the display area.

18 . The display panel according to claim 1 , wherein

a border of the display area and a signal line arrangement region closest thereto are further provided with a common electrode lead line therebetween, and the signal line arrangement region closest to the border of the display area is the first signal line arrangement region or the second signal line arrangement region, wherein

a contour of at least part of the common electrode lead line is the same as an corresponding outer contour of the display area, or

dummy sub-pixels are provided at a periphery of the display area, and the at least part of the common electrode lead line extends to fit an outer contour of a whole composed of sub-pixels and the dummy sub-pixels in the display area.

19 . The display panel according to claim 1 wherein

the first reference lead-out position is a first lead-out position closest to a position of the first signal line arrangement region with a maximum width; and/or

the second reference lead-out position is a second lead-out position closest to a position of the second signal line arrangement region with a maximum width.

20 . The display panel according to claim 1 ,

the display panel comprises a gate driving circuit located in the peripheral area, wherein the gate driving circuit has a plurality of shift register units, at least part of the plurality of shift register units are electrically connected to the gate lines for sending gate driving signals to the gate lines; an overall span of the plurality of shift register units in the second direction is less than an overall span of the pixels in the display area in the second direction; the display panel comprises a data line bonding region, wherein the data line bonding region includes a plurality of data line bonding pins, and the first signal lines are electrically connected to the data line bonding pins in a one-to-one correspondence; wherein

the first signal line arrangement region is located in a region between a non-display area that is between the gate driving circuit in the peripheral area and the display area and a non-display area that is between the data line bonding region and the display area; and

the second signal line arrangement region is located in a region between a non-display area that is between the gate driving circuit in the peripheral area and the display area and a non-display area that is between the data line bonding region and the display area; or

the display panel comprises a data line bonding region, wherein the data line bonding region includes a plurality of data line bonding pins, and the first signal lines are electrically connected to the data line bonding pins in a one-to-one correspondence; and the display panel comprises a gate line bonding region, wherein the gate line bonding region includes a plurality of gate line bonding pins, and the second signal lines are electrically connected to the gate line bonding pins in a one-to-one correspondence; wherein

the first signal line arrangement region is located in a region between a non-display area that is between the gate line bonding region in the peripheral area and the display area and a non-display area that is between the data line bonding region and the display area; and

the second signal line arrangement region is located in a region between a non-display area that is between the gate line bonding region in the peripheral area and the display area and a non-display area that is between the data line bonding region and the display area.