Timing controller and dynamic charge sharing method thereof

1 . A timing controller, comprising:

a power calculator, configured to:

receive pixel data in a first row and a second row on a display panel, wherein the first row and the second row each include a plurality of sub-pixel groups, and each of the sub-pixel groups comprises a plurality of first sub-pixels and a plurality of second sub-pixels;

select different numbers of the first sub-pixels and the second sub-pixels in each sub-pixel group of the first row to define a plurality of charge sharing modes for a source driver;

respectively average the pixel data of the selected first sub-pixels and the selected second sub-pixels in each sub-pixel group of the first row to obtain a first average value and a second average value for each charge sharing mode;

reference each of the first sub-pixels and the second sub-pixels in a second row to a corresponding one of the first sub-pixels and the second sub-pixels in the first row; and

calculate a transition power level for each of the first sub-pixels and the second sub-pixels in the second row under each charge sharing mode by transiting the first average value or the second average value of the corresponding one of the first sub-pixels and the second sub-pixels in the first row into a target pixel data of a target sub-pixel in the second row; and

a mode selector, electrically connected to the power calculator and configured to:

sum the transition power of all first sub-pixels and second sub-pixels in each sub-pixel group in the first row to obtain a total channel power level under each of the charge sharing modes; and

select one of the charge sharing modes with a minimum total channel power level for each of the sub-pixel groups in the first row.

2 . The timing controller of claim 1 , wherein the first sub-pixels are driven by a positive voltage level and the second sub-pixels are driven by a negative voltage level during a current frame.

3 . The timing controller of claim 2 , wherein the first sub-pixels in each sub-pixel group are arranged in odd-numbered columns of the first row and the second row, and the second sub-pixels in each sub-pixel group are arranged in even-numbered columns of the first row and the second row.

4 . The timing controller of claim 2 , wherein the source driver comprises a plurality of driving channels, each of the driving channels comprises a first driving circuit for providing the positive voltage level and a second driving circuit for providing the negative voltage level, the power calculator further configured to:

determine whether the transition between each of the first sub-pixels and the second sub-pixels in the first row and the corresponding one of the first sub-pixels and the second sub-pixels in the second row consumes power or not, wherein the transition power level is determined as a consumed power in response to the first average value being lower than the target pixel data and in response to the second average value being higher than the target pixel data.

5 . The timing controller of claim 4 , wherein a total number of the charge sharing modes is defined as the sum of combinations formed by selecting k1 first sub-pixels from each sub-pixel group and k2 second sub-pixels from each sub-pixel group, where each sub-pixel group comprises n first sub-pixels and n second sub-pixels and k1 and k2 range from 2 to n.

6 . The timing controller of claim 1 , further comprising:

a line buffer electrically connected to the power calculator and configured to store a position information of the first sub-pixels and the second sub-pixels in the first row, wherein the power calculator references the target sub-pixel in the second row to the corresponding one of the first sub-pixels and the second sub-pixels in the first row based on the position information, wherein the corresponding one of the first sub-pixels and the second sub-pixels in the first row are located at an upper-left, an upper-center, or an upper right of the target sub-pixel in the second row.

7 . The timing controller of claim 1 , wherein the display panel is driven by a plurality of source drivers, the timing controller further comprising:

a driver setting circuit electrically connected to the power calculator and configured to set the number of the source drivers.

8 . The timing controller of claim 7 , wherein a number of the sub-pixel groups in each row is depend on a horizontal resolution of the display panel and a total number of source drivers used to drive the display panel.

9 . A dynamic charge sharing control method for a timing controller, comprising:

receiving pixel data in a first row and a second row on a display panel, wherein the first row and the second row each include a plurality of sub-pixel groups, and each of the sub-pixel groups comprises a plurality of first sub-pixels and a plurality of second sub-pixels;

selecting different numbers of the first sub-pixels and the second sub-pixels in each sub-pixel group of the first row to define a plurality of charge sharing modes;

respectively averaging the pixel data of the selected first sub-pixels and the selected second sub-pixels in each sub-pixel group of the first row to obtain a first average value and a second average value for each charge sharing mode;

referencing each of the first sub-pixels and the second sub-pixels in the second row to a corresponding one of the first sub-pixels and the second sub-pixels in the first row;

calculating a transition power level for each of the first sub-pixels and the second sub-pixels in the first row under each charge sharing mode by transiting the first average value or the second average value of the corresponding one of the first sub-pixels and the second sub-pixels in the first row into a target pixel data of a target sub-pixel in the second row;

summing the transition power level of all first sub-pixels and second sub-pixels in each sub-pixel group in the first row to obtain a total channel power level for each sub-pixel group under each charge sharing mode; and

selecting one of the charge sharing modes with a minimum total channel power level for each of the sub-pixel groups in the first row.

10 . The dynamic charge sharing control method of claim 9 , wherein the first sub-pixels are driven by a positive voltage level and the second sub-pixels are driven by a negative voltage level during a current frame.

11 . The dynamic charge sharing control method of claim 10 , wherein the first sub-pixels in each sub-pixel group are arranged in odd-numbered columns of the first row and the second row, and the second sub-pixels in each sub-pixel group are arranged in even-numbered columns of the first row and the second row.

12 . The dynamic charge sharing control method of claim 10 , wherein a source driver comprises a plurality of driving channels, each of the driving channels comprises a first switching circuit for providing the positive voltage level and a second switching circuit for providing the negative voltage level, the dynamic charge sharing control method further comprising:

determining whether the transition between each of the first sub-pixels and the second sub-pixels in the first row and the corresponding one of the first sub-pixels and the second sub-pixels in the second row consumes power or not;

wherein the transition power level is determined as a consumed power in response to the first average value being lower than the target pixel data and in response to the second average value being higher than the target pixel data.

13 . The dynamic charge sharing control method of claim 12 , further comprising:

summing the transition power level of the first sub-pixels and the second sub-pixels in the first row driven by the same driving channel to obtain a channel power level for each of the driving channels; and

summing the channel power level of each of the driving channels to obtain the total channel power level.

14 . The dynamic charge sharing control method of claim 9 , wherein a number of the sub-pixel groups in each row is depend on a horizontal resolution of the display panel and a total number of source drivers used to drive the display panel.

15 . The dynamic charge sharing control method of claim 9 , further comprising:

calculating the transition power level for each of the first sub-pixels and the second sub-pixels in the second row without charge sharing by transiting the pixel data of each of the first sub-pixels and the second sub-pixels in the first row into the target pixel data of the corresponding one of the first sub-pixels and the second sub-pixels in the second row;

summing the transition power level of all first sub-pixels and second sub-pixels in each sub-pixel group of the first row to obtain the total channel power level without charge sharing; and

selecting the one with the minimum total channel power level between no charge sharing and the charge sharing modes for each of the sub-pixel groups in the second row.

16 . The dynamic charge sharing control method of claim 9 , wherein the step of referencing each of the first sub-pixels and the second sub-pixels in the second row to the corresponding one of the first sub-pixels and the second sub-pixels in the first row further comprising:

obtaining a position information for the first sub-pixels and the second sub-pixels in the first row; and

referencing the target sub-pixel in the second row to the corresponding one of the first sub-pixels and the second sub-pixels in the first row based on the position information, wherein the corresponding one of the first sub-pixels and the second sub-pixels in the first row are located at an upper-left, an upper-center, or an upper right of the target sub-pixel in the second row.

17 . The dynamic charge sharing control method of claim 9 , wherein a total number of the charge sharing modes is defined as the sum of combinations formed by selecting k1 first sub-pixels from each sub-pixel group and k2 second sub-pixels from each sub-pixel group, where each sub-pixel group comprises n first sub-pixels and n second sub-pixels, and k1 and k2 range from 2 to n.