Memory device

Inventors: Chen-Yu Cheng (Hsinchu City, TW); Tzung-Ting Han (Hsinchu City, TW)

Assignee: Macronix International Co., Ltd.

G11C8/14 H10B41/10 H10B41/27 H10B41/35 H10B41/41 H10B43/10 H10B43/27 H10B43/35 H10B43/40

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12670941
App. No.: 18/319,834
Granted: Jun 30, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

Claims (32)

1 . A memory device, comprising:

a substrate having a staircase region, a word line cutting region and a memory array region, wherein the memory array region is located between the staircase region and the word line cutting region;

a stack structure in the memory array region, wherein the stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other;

a first staircase structure located in the staircase region, wherein the first staircase structure comprises the plurality of first insulating layers and the plurality of conductive layers stacked alternately on each other;

a second staircase structure located in the word line cutting region, wherein the second staircase structure comprises the plurality of first insulating layers and the plurality of conductive layers stacked alternately on each other, and the second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region; and

block slits and zone slits disposed over the substrate in the word line cutting region, wherein the block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks, and the zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks,

wherein a width of the word line cutting region is less than a width of the staircase region.

2 . The memory device according to claim 1 , wherein a number of steps of the second staircase structure is less than a number of steps of the first staircase structure.

3 . The memory device according to claim 1 , wherein the second staircase structure is a dummy staircase structure.

4 . The memory device according to claim 1 , wherein no contact plug is formed in the second staircase structure.

5 . The memory device according to claim 4 , further comprising a plurality of first contacts respectively connected to the plurality of conductive layers of the first staircase structure.

6 . The memory device according to claim 1 , wherein the substrate further has a periphery region adjacent to the word line cutting region, and the word line cutting region is located between the memory array region and the periphery region, and

the plurality of first insulating layers and the plurality of conductive layers stacked alternately on each other having steps descending in the word line cutting region are a first part of the second staircase structure, and the plurality of first insulating layers and a plurality of second insulating layers stacked alternately on each other in the periphery region are a second part of the second staircase structure and have steps ascending from the lower layer proximal to the first part to the upper layer distal from the first part.

7 . The memory device according to claim 6 , wherein the plurality of conductive layers in the first part of the second staircase structure are separated from the plurality of second insulating layers in the second part of the second staircase structure.

8 . The memory device according to claim 1 , wherein the plurality of conductive layers of the first staircase structure are connected to the plurality of conductive layers of the stack structure and the plurality of conductive layers of the second staircase structure.

9 . The memory device according to claim 1 , further comprising a device layer under the stack structure and over the substrate.

10 . The memory device according to claim 1 , wherein a trench extends along a direction at an end of each of the second staircase structure in two adjacent zones.

11 . A memory device comprising:

a substrate having a staircase region, a word line cutting region and a memory array region, wherein the memory array region is located between the staircase region and the word line cutting region;

a stack structure in the memory array region, wherein the stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other;

a second staircase structure located in the word line cutting region, wherein the second staircase structure comprises the plurality of first insulating layers and the plurality of conductive layers stacked alternately on each other, and has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region; and

at least two block slits and at least one zone slit disposed over the substrate in the word line cutting region, wherein the at least two block slits divide the stack structure, the first staircase structure and the second staircase structure to define a memory block, and the at least one zone slit divides the memory block into two adjacent zones within the memory block separately,

wherein a width of the word line cutting region is less than a width of the staircase region.

12 . The memory device according to claim 11 , wherein a number of steps of the second staircase structure is less than a number of steps of the first staircase structure.

13 . The memory device according to claim 11 , wherein no contact plug is formed in the second staircase structure.

14 . The memory device according to claim 13 , further comprising a plurality of first contacts respectively connected to the plurality of conductive layers of the first staircase structure.

15 . The memory device according to claim 11 , further comprising a device layer under the stack structure and over the substrate.

16 . The memory device according to claim 11 , wherein the substrate further has a periphery region adjacent to the word line cutting region, and the word line cutting region is located between the memory array region and the periphery region, and

17 . The memory device according to claim 16 , wherein the plurality of conductive layers in the first part of the second staircase structure are separated from the plurality of second insulating layers in the second part of the second staircase structure.

18 . The memory device according to claim 16 , wherein a side profile of the second part of the second staircase structure is symmetrical with a side profile of the first part of the second staircase structure.