Plate-line assist memory
Described herein is a method and apparatus to reduce electric displacement and polarization target for a memory bit-cell. In at least one embodiment, the apparatus comprises one or more circuitries to adjust voltage on a plate-line to be above or below a nominal voltage of the plate-line based on a write operation or read operation on a bit-cell. In at least one embodiment, the bit-cell comprises a transistor and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to the plate-line and a second terminal coupled to the transistor.
1 . An apparatus comprising:
one or more circuitries to adjust a voltage on a plate-line to be above or below a nominal supply voltage of the plate-line based on a write operation or read operation on a bit-cell, wherein the one or more circuitries include:
a fly-capacitor;
a first pass-gate coupled to a supply rail and a first terminal of the fly-capacitor;
a second pass-gate coupled to a ground rail and the first terminal of the fly-capacitor; and
a second driver coupled to a second terminal of the fly-capacitor, wherein the bit-cell comprises:
a transistor; and
a capacitor which includes non-linear polar material, wherein the capacitor has a first terminal coupled to the plate-line and a second terminal coupled to the transistor.
2 . The apparatus of claim 1 , wherein the nominal supply voltage is a supply voltage in a write 1 operation.
3 . The apparatus of claim 1 , wherein the nominal supply voltage is a ground voltage in a write 0 operation.
4 . The apparatus of claim 1 , wherein the one or more circuitries is to adjust the voltage by an amount substantially equal to a threshold voltage of the transistor.
5 . The apparatus of claim 1 , wherein the nominal supply voltage is a ground voltage, and wherein the one or more circuitries is to decrease the voltage on the plate-line below the ground voltage in a write 1 logic operation.
6 . The apparatus of claim 1 , wherein the nominal supply voltage is a supply voltage, and wherein the one or more circuitries is to increase the voltage on the plate-line above the supply voltage in a write 0 logic operation.
7 . The apparatus of claim 1 , wherein the transistor has a gate terminal coupled to a word-line, and wherein the one or more circuitries is to increase a voltage on the word-line in the write operation or the read operation.
8 . The apparatus of claim 1 , wherein the transistor is coupled to a bit-line, wherein the bit-line is parallel to the plate-line, or wherein the plate-line is parallel to a word-line, and wherein the word-line is coupled to the transistor.
9 . The apparatus of claim 1 , wherein the one or more circuitries include:
a driver having an output coupled to the plate-line;
a pull-up transistor coupled to the supply rail of the driver, and also coupled to a second supply rail; and
a pull-down transistor coupled to the ground rail of the driver, and also coupled to a second ground rail.
10 . The apparatus of claim 1 , wherein a output is coupled to a plurality of plate-lines including the plate-line.
11 . The apparatus of claim 1 , wherein the non-linear polar material is one of a ferroelectric, a paraelectric, or a non-linear dielectric material.
12 . The apparatus of claim 1 , wherein the non-linear polar material is doped with one or more elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of a periodic table.
13 . The apparatus of claim 1 , wherein the non-linear polar material includes one of:
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO);
barium titanate (BTO);
BFO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
BTO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
LBFO doped with Mn;
lead zirconium titanate (PZT) or PZT with a first doping material, wherein the first doping material is one of La, Nb, Mn, or 5d series elements;
bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of the periodic table;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides such as Hf (1-x) E x O y , where E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100, or
a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric; or
a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or a PMN-PT based relaxor ferroelectric.
14 . An apparatus comprising:
one or more circuitries to adjust voltage on a plate-line of a bit-cell to be above or below a nominal supply voltage of the plate-line based at least in part on a write operation, writeback operation, or read operation on the bit-cell, wherein the one or more circuitries include:
a fly-capacitor;
a first pass-gate coupled to a supply rail and a first terminal of the fly-capacitor;
a second pass-gate coupled to a ground rail and the first terminal of the fly-capacitor; and
a second driver coupled to a second terminal of the fly-capacitor.
15 . The apparatus of claim 14 , wherein the nominal supply voltage is a ground voltage, and wherein the one or more circuitries is to decrease the voltage on the plate-line below the ground voltage in a write 1 logic operation.
16 . The apparatus of claim 14 , wherein the nominal supply voltage is a supply voltage, and wherein the one or more circuitries is to increase the voltage on the plate-line above the supply voltage in a write 0 logic operation.
17 . The apparatus of claim 14 , wherein the one or more circuitries is to increase a voltage on a word-line in of the bit-cell in the write operation or the read operation.
18 . A system comprising:
a processor circuitry;
a memory coupled to the processor circuitry; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
one or more circuitries to adjust a voltage on a plate-line to be above or below a nominal supply voltage of the plate-line based on a write operation or read operation on a bit-cell, wherein the one or more circuitries include:
a fly-capacitor;
a first pass-gate coupled to a supply rail and a first terminal of the fly-capacitor;
a second pass-gate coupled to a ground rail and the first terminal of the fly-capacitor; and
a second driver coupled to a second terminal of the fly-capacitor, wherein the bit-cell comprises:
a transistor; and
a capacitor which includes non-linear polar material, wherein the capacitor has a first terminal coupled to the plate-line and a second terminal coupled to the transistor.
19 . The system of claim 18 , wherein the nominal supply voltage is a ground voltage, and wherein the one or more circuitries is to decrease the voltage on the plate-line below the ground voltage in a write 1 logic operation.