Memory device and operating method thereof for applying voltage to transistor based on output of memory cell
A memory device including: a first cell including a first transistor and a capacitor connected to the first transistor and storing a voltage corresponding to data; a second cell including a second transistor; a voltage generation circuit for applying voltages to the source, gate, and drain of the second transistor and to the gate and back gate of the first transistor; a measuring circuit connected to the second cell, measuring at least one of a current and a voltage output from the second cell, and generating a leakage value based on at least one value of the measured current and voltage; and a monitoring circuit connected to the measuring circuit, calculating a threshold voltage of the second transistor based on the leakage value, and generating a control signal for controlling the voltage generation circuit based on the threshold voltage.
1 . A memory device, comprising:
a first cell including a first transistor and a capacitor connected to the first transistor, the capacitor storing a voltage corresponding to data;
a second cell including a second transistor;
a voltage generation circuit configured to apply respective voltages to a source, a gate, and a drain of the second transistor, and to a gate and a back gate of the first transistor;
a measuring circuit connected to the second cell, the measuring circuit configured to measure a current and/or a voltage output from the second cell, and to generate a leakage value based on at least one parameter of the current and/or voltage that was measured; and
a monitoring circuit connected to the measuring circuit, the monitoring circuit configured to calculate a threshold voltage of the second transistor based on a measured voltage of the drain of the second transistor, a current value supplied by a current source to the drain of the second transistor, and a source voltage applied to the source of the second transistor, and to generate a control signal for controlling the voltage generation circuit as a function of the threshold voltage.
2 . The memory device of claim 1 , wherein:
the voltage generation circuit is configured to apply a source voltage corresponding to a first voltage to the source of the second transistor, a gate voltage corresponding to a second voltage higher than the first voltage to the gate of the second transistor, and a drain voltage corresponding to a third voltage higher than the second voltage to the drain of the second transistor, and
the current is a dynamic leakage current of the second cell.
3 . The memory device of claim 1 , wherein:
the voltage generation circuit is configured to apply a source voltage corresponding to a first voltage to the source of the second transistor, a gate voltage corresponding to a second voltage lower than the first voltage to the gate of the second transistor, and a drain voltage corresponding to a third voltage higher than the first voltage to the drain of the second transistor, and
the current is a static leakage current of the second cell.
4 . The memory device of claim 1 , wherein:
the voltage generation circuit is configured to apply a source voltage corresponding to a first voltage to the source of the second transistor, a gate voltage corresponding to a second voltage lower than the first voltage to the gate of the second transistor, and a drain voltage corresponding to a third voltage lower than the second voltage to the drain of the second transistor, and
the current is a gate leakage current of the second cell.
5 . The memory device of claim 1 , wherein:
the gate of the second transistor and the drain of the second transistor are connected together, and the current source is connected to the drain of the second transistor, and
the measuring circuit includes an analog-to-digital converter connected to the drain of the second transistor and is configured to measure the voltage of the drain of the second transistor to generate the leakage value.
6 . The memory device of claim 1 , wherein
the voltage generation circuit is configured to alternately apply a first voltage and a second voltage lower than the first voltage to the gate of the second transistor.
7 . The memory device of claim 1 , wherein
the monitoring circuit is configured to generate the control signal so that the first transistor has a target threshold voltage based at least in part on a difference between the threshold voltage of the second transistor and a predetermined target threshold voltage.
8 . The memory device of claim 7 , wherein
the control signal is configured to control the voltage generation circuit so as to apply a back gate voltage to the back gate of the first transistor based at least in part on the difference between the target threshold voltage and the threshold voltage.
9 . The memory device of claim 8 , wherein
the control signal is configured to control the voltage generation circuit so that a gate voltage applied to the gate of the first transistor is included within a predetermined range with reference to the target threshold voltage.
10 . The memory device of claim 9 , wherein:
the monitoring circuit is configured to set a first gate voltage for turning off the first transistor and a second gate voltage for turning on the first transistor, and
the first gate voltage is less than or equal to a predetermined first voltage with reference to the target threshold voltage, and the second gate voltage is greater than or equal to a predetermined second voltage with reference to the target threshold voltage.
11 . The memory device of claim 1 , wherein:
the measuring circuit includes an operational amplifier connected to the drain of the second transistor, a first PMOS transistor including a gate connected to an output terminal of the operational amplifier, a first source/drain connected to a voltage source, and a second source/drain connected to the drain of the second transistor, a second PMOS transistor including a gate connected to the output terminal of the operational amplifier, a first source/drain connected to the voltage source, and a second source/drain connected to a first node, and a resistor including a first terminal connected to the first node and a second terminal connected to ground, and
the monitoring circuit is connected to the first node.
12 . The memory device of claim 1 , wherein:
the measuring circuit includes an operational amplifier connected to the gate of the second transistor, a first PMOS transistor including a gate connected to an output terminal of the operational amplifier, a first source/drain connected to a voltage source, and a second source/drain connected to a drain of the second transistor, a second PMOS transistor including a gate connected to the output terminal of the operational amplifier, a first source/drain connected to the voltage source, and a second source/drain connected to a first node, and a resistor including a first terminal connected to the first node and a second terminal connected to ground, and
the monitoring circuit is connected to the first node.
13 . A driving method of a memory device, the method comprising:
applying a predetermined voltage to a source, a drain, and a gate of a first transistor;
measuring a voltage applied to the first transistor and/or a current flowing in the first transistor;
calculating a threshold voltage of the first transistor based on a measured voltage of the drain of the first transistor, a current value supplied by a current source to the drain of the first transistor, and a source voltage applied to the source of the first transistor; and
setting a back gate voltage applied to a back gate of a second transistor in the memory device based on a difference between a predetermined target threshold voltage for the second transistor and the threshold voltage of the first transistor.
14 . The driving method of the memory device of claim 13 , further comprising
setting a first gate voltage for turning off the second transistor and a second gate voltage for turning on the second transistor,
wherein the first gate voltage is less than or equal to a predetermined first voltage with reference to the predetermined target threshold voltage, and the second gate voltage is greater than or equal to a predetermined second voltage with reference to the predetermined target threshold voltage.
15 . The driving method of the memory device of claim 13 , wherein
applying the predetermined voltage includes
alternately applying a first voltage and a second voltage lower than the first voltage to the gate of the first transistor.
16 . The driving method of the memory device of claim 13 , wherein
applying the predetermined voltage includes
applying a source voltage corresponding to a first voltage to the source of the first transistor, a gate voltage corresponding to a second voltage higher than the first voltage to the gate of the first transistor, and a drain voltage corresponding to a third voltage higher than the second voltage to the drain of the first transistor.
17 . The driving method of the memory device of claim 13 , wherein
applying the predetermined voltage includes
applying a source voltage corresponding to a first voltage to the source of the first transistor, a gate voltage corresponding to a second voltage lower than the first voltage to the gate of the first transistor, and a drain voltage corresponding to a third voltage higher than the first voltage to the drain of the first transistor.
18 . The driving method of the memory device of claim 13 , wherein
applying the predetermined voltage includes
applying a source voltage corresponding to a first voltage to the source of the first transistor, a gate voltage corresponding to a second voltage lower than the first voltage to the gate of the first transistor, and a drain voltage corresponding to a third voltage lower than the second voltage to the drain of the first transistor.
19 . The driving method of the memory device of claim 13 , further comprising
setting a gate voltage of the second transistor so that the gate voltage applied to a gate of the second transistor is included within a predetermined range with reference to the predetermined target threshold voltage.
20 . A memory system, comprising:
a memory device including a first cell including a first transistor and a capacitor connected to the first transistor, the capacitor configured to store a voltage corresponding to data, and a second cell including a second transistor; and
a memory controller configured to provide an external voltage to the memory device,
wherein the memory device is configured to:
based on the provided external voltage, select, from a pre-determined voltage condition set, a first pre-determined voltage condition,
apply a voltage to the second transistor according to the first pre-determined voltage condition selected based on the external voltage, and set a voltage applied to the first transistor based at least in part on a current and/or a voltage output from the second cell.