Apparatuses and methods for tracking word line accesses
A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.
1 . An apparatus comprising:
a word line comprising a plurality of count value memory cells configured to store an access count, wherein the access count represents a value indicating a number of times the word line has been accessed and a length of time the word line is active;
a timer circuit configured to provide a periodic signal responsive, at least in part, to an activation signal;
a counter circuit configured to change the access count responsive, at least in part, to the periodic signal and provide an updated access count value to the plurality of count value memory cells;
an oscillator configured to provide the periodic signal responsive to an active enable signal; and
a delay circuit configured to receive the activation signal and provide the active enable signal to the oscillator.
2 . The apparatus of claim 1 , wherein a period of the periodic signal is programmable by providing a period trim key to the oscillator and a delay of the delay circuit is programmable by providing a delay trim key to the delay circuit.
3 . The apparatus of claim 2 , wherein the period trim key, the delay trim key, or both are provided from a fuse array or a mode register.
4 . The apparatus of claim 1 , further comprising a logic circuit configured to receive the periodic signal from the oscillator and the activation signal, wherein the logic circuit is configured to provide the periodic signal to the counter circuit when the activation signal is active.
5 . The apparatus of claim 1 , further comprising a comparator circuit configured to compare the access count value, the updated access count value, or both to a threshold value.
6 . The apparatus of claim 5 , wherein the comparator circuit is configured to activate a trigger signal based on a comparison of the access count value, the updated access count value, or both to the threshold value.
7 . A method comprising:
receiving an external activation command at a memory;
responsive, at least in part, to the external activation command, enabling an oscillator circuit to provide a periodic signal;
changing a count value responsive to the periodic signal;
reading an access count from a word line, wherein the access count represents a value indicating a number of times the word line has been accessed and a length of time the word line is active;
combining the count value and the access count to generate an updated access count;
writing the updated access count to the word line;
receiving an external precharge command; and
disabling the oscillator responsive, at least in part, to the external precharge command.
8 . The method of claim 7 , wherein the reading the access count from the word line is performed responsive to the external precharge command.
9 . The method of claim 7 , wherein the writing the updated access count to the word line is performed responsive to the external precharge command.
10 . The method of claim 7 , wherein the reading the access count from the word line is performed responsive, at least in part, to the external activation command.
11 . The method of claim 7 , wherein the combining and the writing are performed each time the count value is changed.
12 . A method comprising:
receiving an external activation command at a memory;
responsive, at least in part, to the external activation command, enabling an oscillator circuit to provide a periodic signal;
changing a count value responsive to the periodic signal;
reading an access count from a word line, wherein the access count represents a value indicating a number of times the word line has been accessed and a length of time the word line is active;
combining the count value and the access count to generate an updated access count;
writing the updated access count to the word line; and
delaying the enabling of the oscillator.
13 . A method comprising:
receiving an external activation command at a memory;
responsive, at least in part, to the external activation command, enabling an oscillator circuit to provide a periodic signal;
changing a count value responsive to the periodic signal;
reading an access count from a word line, wherein the access count represents a value indicating a number of times the word line has been accessed and a length of time the word line is active;
combining the count value and the access count to generate an updated access count;
writing the updated access count to the word line; and
setting a period of the periodic signal with a trim key.
14 . A memory device comprising:
a memory array comprising a plurality of word lines, each comprising at least one count value memory cell configured to store an access count that represents a value indicating a number of times a respective word line of the plurality of word lines has been accessed and a length of time the respective word line is active;
a refresh control circuit configured to selectively cause ones of the plurality of word lines to be refreshed; and
a count control circuit configured to read the access count, update the access count, and write an updated access count to the respective word line of the plurality of word lines, wherein the count control circuit comprises:
a timer configured to be enabled by an activation command and disabled by a precharge command; and
a counter configured to update the access count based, at least in part, on a periodic signal provided by the timer when enabled.
15 . The memory device of claim 14 , wherein the count control circuit is further configured to compare the access count, the updated access count, or both to a threshold value and provide a signal to the refresh control signal based on a comparison of the access count, the updated access count, or both to the threshold value.
16 . The memory device of claim 14 , wherein a row precharge time ((RP) of the memory device is equal to or greater than a write recovery time (tWR) of the memory device that allows the updated access count to be written to the respective word line.
17 . The memory device of claim 14 , wherein a period of the periodic signal is programmable.
18 . The memory device of claim 14 , wherein the periodic signal may be delayed by an amount indicated by a trim key.