Bit cell based write self-time delay path
The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.
1 . A device, comprising:
a first bit line;
a second bit line;
a write self-time bit cell electrically coupled between the first bit line and the second bit line and including a first invert and a second inverter cross-coupled together between a high-supply node and ground;
a write inverter electrically coupled to the first bit line, the write inverter configured to receive a write in signal;
a write detect inverter having an input electrically coupled to the high supply node of the write self-time bit cell, the write detect inverter configured to output a write detect signal;
an input voltage transistor having a source terminal coupled to a high supply voltage, a drain terminal coupled to the high supply node, and a gate terminal coupled to receive a first control signal; and
a ground transistor having a source terminal coupled to ground, a drain terminal coupled to the high supply node, and a gate terminal coupled to receive a second control signal.
2 . The device of claim 1 wherein the input voltage transistor is a p-type transistor, and the ground transistor is an n-type transistor.
3 . The device of claim 1 wherein the write self-time bit cell has a first circuit arrangement including:
a first word line transistor electrically coupled between the first bit line and an output of the first inverter;
a first storing transistor of the first inverter electrically coupled between the high supply voltage node and the output of the first inverter;
a second storing transistor electrically coupled to the output of the first inverter and ground;
a second word line transistor electrically coupled between the second bit line and an output of the second inverter;
a third storing transistor electrically coupled between the high supply node and the output of the first inverter; and
a fourth storing transistor electrically coupled between the output of the first inverter and ground.
4 . The device of claim 3 wherein control terminals of the first storing transistor and the second storing transistor are electrically coupled to the output of the second inverter.
5 . The device of claim 3 wherein control terminals of the third storing transistor and the fourth storing transistor are electrically coupled to the output of the first inverter.
6 . The device of claim 3 wherein the first storing transistor and the third storing transistor are p-type transistors, and the second storing transistor and the fourth storing transistor are n-type transistors.
7 . The device of claim 3 wherein the first word line transistor and the second word line transistor are n-type transistors.
8 . The device of claim 3 , further comprising:
a memory array including a plurality of bit cells, each of the plurality of bit cells have a second circuit arrangement that is the same as the first circuit arrangement.
9 . The device of claim 1 , further comprising:
a memory array including a plurality of bit cells, each of the plurality of bit cells having the same circuit arrangement as the write self-time bit cell.
10 . The device of claim 3 wherein control terminals of the first word line transistor and the second word line transistor are configured to receive a word line signal.
11 . A device comprising:
a first bit line;
a second bit line;
a plurality of write self-time bit cells electrically coupled between the first bit line and the second bit line, the plurality of write self-time bit cells being electrically coupled to each other in parallel, each write self-time bit cell including a first invert and a second inverter cross-coupled together between a high-supply node and ground;
a write inverter electrically coupled to the first bit line, the write inverter configured to receive a write in signal;
a write detect inverter having an input electrically coupled to respective high supply nodes of the plurality of write self-time bit cells, the write detect inverter configured to output a write detect signal;
a plurality of input voltage transistors electrically each having a source terminal coupled to respective high supply nodes of the plurality of write self-time bit cells and high supply voltage; and
a plurality of ground transistors electrically each having a source terminal coupled to ground, a drain terminal coupled to a respective high supply node, and a gate terminal coupled to receive a second control signal.
12 . The device of claim 11 wherein each of the plurality of write self-time bit cell has a first circuit arrangement including:
a first word line transistor electrically coupled between the first bit line and an output of the first inverter;
a first storing transistor of the first inverter electrically coupled between the high supply voltage node and the output of the first inverter;
a second storing transistor electrically coupled to the output of the first inverter and ground;
a second word line transistor electrically coupled between the second bit line and an output of the second inverter;
a third storing transistor electrically coupled between the high supply node and the output of the first inverter; and
a fourth storing transistor electrically coupled between the output of the first inverter and ground.
13 . The device of claim 12 , further comprising:
a memory array including a plurality of bit cells, each of the plurality of bit cells have a second circuit arrangement that is the same as the first circuit arrangement.
14 . The device of claim 11 , further comprising:
a memory array including a plurality of bit cells, each of the plurality of bit cells having the same circuit arrangement as each of the plurality of write self-time bit cells.
15 . A device, comprising:
a first bit line;
a second bit line;
a write self-time bit cell electrically coupled between the first bit line and the second bit line and including a first invert and a second inverter cross-coupled together between a high-supply node and ground;
a write inverter electrically coupled to the first bit line, the write inverter configured to receive a write in signal;
a write detect inverter having an input electrically coupled to the high supply node of the write self-time bit cell, the write detect inverter configured to output a write detect signal;
an input voltage transistor having a source terminal coupled to a high supply voltage, a drain terminal coupled to the high supply node, and a gate terminal coupled to receive a first control signal;
a ground transistor having a source terminal coupled to ground, a drain terminal coupled to the high supply node, and a gate terminal coupled to receive a second control signal;
a memory array including a plurality of bit cells, each of the plurality of bit cells having the same circuit arrangement as the write self-time bit cell; and
a controller configured to control a write operation to at least one of the plurality of bit cells based on the write detect signal.
16 . The device of claim 15 wherein the controller is configured to stop the write operation to at least one of the plurality of bit cells based on the write detect signal.
17 . The device of claim 15 wherein the write self-time bit cell has a circuit arrangement including:
a first word line transistor electrically coupled between the first bit line and an output of the first inverter;
a first storing transistor of the first inverter electrically coupled between the high supply voltage node and the output of the first inverter;
a second storing transistor electrically coupled to the output of the first inverter and ground;
a second word line transistor electrically coupled between the second bit line and an output of the second inverter;
a third storing transistor electrically coupled between the high supply node and the output of the first inverter; and
a fourth storing transistor electrically coupled between the output of the first inverter and ground.
18 . The device of claim 17 wherein control terminals of the first storing transistor and the second storing transistor are electrically coupled to the output of the second inverter.
19 . The device of claim 17 wherein control terminals of the third storing transistor and the fourth storing transistor are electrically coupled to the output of the first inverter.
20 . The device of claim 17 wherein the first storing transistor and the third storing transistor are p-type transistors, and the second storing transistor and the fourth storing transistor are n-type transistors.