The unit to count the storage capacity of the current computing is bit. Hence, the number of transistors (cells) which serve as nodes, that is, the bit number is the unit of the current information communication. On the contrary, the human brain is composed of the cranial nerve circuit. Hence, the memory capacity of the human being is not based on the number of cranial nerves (node number). The complication of the circuit is greater than the bit capacity even with the same node number. The modern artificial intelligence, which tries to reproduce the human brain using the computing based on the bit unit, processes information in an inherently different manner from the human brain. Hence, it is inherently wasteful. Furthermore, the computing based on the bit number is always facing the limitation of integration.
1 . A semiconductor device, comprising:
a plurality of islands arrayed in a first direction and a second direction on a surface of semiconductor, wherein each island has a diffusion layer formed on the said surface of the semiconductor;
first links arrayed such that each of the first links is between two respective islands of the plurality of islands that are adjacent to each other along the first direction, wherein each of the first links comprises a first select gate bridging two islands of the plurality of islands and having a select gate contact;
second links arrayed such that each of the second links is between two respective islands of the plurality of islands that are adjacent to each other along the second direction, wherein each of the second links comprises a second select gate bridging two islands of the plurality of islands and having a select gate contact;
first word lines, each extending along a third direction that may be the same as or different from the first direction;
second word lines, each extending along a fourth direction that may be the same as or different from the second direction, wherein each select gate contact of the first and second links is selected by at least one of the first word lines and one of the second word lines.
2 . The semiconductor device according to claim 1 , wherein each of first and second select gates is a transistor having a first terminal in one island of the plurality of islands and a second terminal in another island of the plurality of islands.
3 . The semiconductor device according to claim 1 , further comprising:
a junction transistor, wherein
the said junction transistor has a junction gate and two terminals,
the said junction gate is connected to one of the said first word lines,
one of the said two terminals is connected to one of the said second word lines, and
the other of the said two terminals is connected to a respective one of the select gate contacts.
4 . The semiconductor device according to claim 1 , further comprising:
two junction transistors which are connected in series with each other, wherein
each of the said two junction transistors has a junction gate and two terminals,
one of the said two junction gates is connected to one of the said first word lines,
the other of the said two junction gates is connected to one of the said second word lines, and
one of the two terminals of one of the said two junction transistors is connected to a respective one of the select gate contacts.
5 . The semiconductor device according to claim 1 , wherein
the first word lines are on a first wiring layer, and
the second word lines are is on a second wiring layer.
6 . The semiconductor device according to claim 1 , further comprising:
a bit line and a third select gate, wherein
the said third select gate has a select gate contact and two terminals,
one of the two terminals of the said third select gate is connected to the said bit line and serves as a bit line contact,
the other of the two terminals of the said third select gate is connected to one of the said plural islands, and
the said select gate contact of the third select gate is selected by the said first and second word lines.
7 . The semiconductor device according to claim 6 , further comprising:
an operational amplifier, wherein
the said operational amplifier is connected to the said bit line, compares a potential of the said bit line with a predetermined threshold voltage, outputs data 1 if the potential of the said bit line is higher than the said threshold potential or outputs data 0 if the potential of the said bit line is lower than the said threshold potential.
8 . The semiconductor device according to claim 7 , further comprising:
a first and second bit-line select gates, and a source line, wherein
the said first bit line select gate is between the said bit line contact and the said operational amplifier, and
the said second bit line select gate is between the said bit line contact and the said source line.
9 . The semiconductor device according to claim 8 , further comprising:
a capacitor, wherein
the said capacitor is between the said first and second bit-line select gates and is connected to the said bit line.