Self-supporting SGD stadium
A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.
1 . A memory device comprising:
an array of vertical memory cells arranged in tiers;
drain-end select gate (SGD) transistors coupled to the array;
a pillar progression of levels of pillars, with each pillar of one level structured on and extending vertically from a different pillar of a level on which the one level is located except for each pillar of a bottom level of the pillar progression, the pillar progression providing support for the tiers of vertical memory cells and the SGD transistors; and
a SGD stadium having conductive steps coupled to the SGD transistors such that the SGD stadium is dedicated to the conductive steps to the SGD transistors, the SGD stadium located within at least a portion of the pillar progression.
2 . The memory device of claim 1 , wherein the pillar progression includes a level of pillars dedicated to the SGD stadium and structured as a top level of the pillar progression and one or more levels of pillars arranged for the array of vertical memory cells.
3 . The memory device of claim 1 , wherein levels of pillars of the pillar progression, structured to support the array of vertical memory cells, are located under the SGD stadium.
4 . The memory device of claim 1 , wherein the pillar progression is an extension of pillars of the array.
5 . The memory device of claim 1 , wherein horizontal extent of the SGD stadium is entirely located within the pillar progression.
6 . The memory device of claim 5 , wherein the memory device includes:
block select circuitry positioned below a bottom level of the pillar progression to one side of a portion of the memory array; and
SGD drivers are positioned below the bottom level of the pillar progression under the portion of the memory array.
7 . The memory device of claim 1 , wherein a middle section of the SGD stadium or a side of the SGD stadium without electrical coupling for the SGD transistors is arranged to position metal entry to carry signals to one or more circuits below a bottom level of the pillar progression.
8 . A memory device comprising:
an array of vertical memory cells arranged in tiers;
drain-end select gate (SGD) transistors coupled to the array;
a pillar progression of levels of pillars extending vertically above a substrate, the levels of pillars arranged horizontally into multiple sections, with each pillar of one level structured on and extending vertically from a different pillar of a level on which the one level is located except for each pillar of a bottom level of the pillar progression, the pillar progression providing support for tiers of vertical memory cells and the SGD transistors;
a SGD stadium having conductive steps coupled to the SGD transistors such that the SGD stadium is dedicated to the conductive steps to the SGD transistors, the SGD stadium located within at least a portion of the pillar progression; and
SGD contacts arranged in the multiple sections of the pillar progression within the at least a portion of the pillar progression.
9 . The memory device of claim 8 , wherein SGD contacts in each tread of the SGD stadium are placed in-line or staggered according to proximity rules for integration and design.
10 . The memory device of claim 8 , wherein the memory device includes a circuit-under-array region on which the array is located, with the SGD transistors coupled to one or more circuits in the circuit-under-array region via the SGD stadium.
11 . The memory device of claim 8 , wherein the pillar progression includes a level of pillars dedicated to the SGD stadium and structured as a top level of the pillar progression and one or more levels of pillars arranged to support the array of vertical memory cells and located below a bottom level of the SGD stadium.
12 . The memory device of claim 8 , wherein horizontal extent of the SGD stadium is entirely located within the pillar progression.
13 . A method of forming a memory device, the method comprising:
forming an array of vertical memory cells arranged in tiers;
forming drain-end select gate (SGD) transistors coupled to the array;
forming a pillar progression of levels of pillars, with each pillar of one level structured on and extending vertically from a different pillar of a level on which the one level is located except for each pillar of a bottom level of the pillar progression, the pillar progression providing support for the tiers of vertical memory cells and the SGD transistors; and
forming a SGD stadium having a conductive step coupled to the SGD transistors such that the SGD stadium is dedicated to the conductive steps to the SGD transistors, including locating the SGD stadium within at least a portion of the pillar progression.
14 . The method of claim 13 , wherein forming the pillar progression includes forming a level of pillars dedicated to the SGD stadium and structured as a top level of the pillar progression and forming one or more levels of pillars arranged as supports in forming the array of vertical memory cells.
15 . The method of claim 14 , wherein the method includes forming the one or more levels of pillars, arranged as supports, to a height below a level for forming the SGD stadium.
16 . The method of claim 13 , wherein the method includes forming the SGD stadium having a horizontal extent entirely located within the pillar progression.
17 . A method of forming a memory device, the method comprising:
forming a portion of a pillar progression of levels of pillars through alternating regions of a first dielectric material and a second dielectric material, the alternating regions formed extending above a substrate, with each pillar of one level structured on and extending vertically from a different pillar of a level on which the one level is located except for each pillar of a bottom level of the pillar progression;
forming a first stadium, dedicated to drain-end select gate (SGD) transistors to couple to an array of vertical memory cells, in the alternating regions above at least a portion of the pillar progression;
forming multiple stadia in the alternating regions adjacent to the pillar progression;
forming an additional level of pillars to the portion of the pillar progression, with each pillar of the additional level structured on and extending vertically from a different pillar of a level on which the additional level is located; and
forming contact structures in the first stadium to couple to the SGD transistors.
18 . The method of claim 17 , wherein the method includes performing, after forming the additional level of pillars on the portion of the pillar progression, a replacement gate process to form gates to memory cells and the SGD transistors.
19 . The method of claim 17 , wherein the method includes forming the first stadium shallower than each of the multiple stadia and dedicating the first stadium to the SGD transistors with the SGD transistors arranged in different tiers.
20 . The method of claim 17 , wherein the method includes forming metal entry to carry signals to one or more circuits below a bottom level of the pillar progression, including positioning the metal entry in a middle section of the first stadium or in a side of the first stadium structured without electrical coupling for other regions of the memory device.