IP Library › Granted Patent US 12670957

Granted Patent B2

US 12670957 · App. 18/631,556 · Granted Jun 30, 2026

Semiconductor memory device

Inventor: Hiroshi Maejima (Tokyo, JP)

Assignee: Kioxia Corporation

G11C16/0483 G11C16/08 G11C16/10 G11C16/26 G11C16/16

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Quick Facts

Patent No.: US 12670957
App. No.: 18/631,556
Granted: Jun 30, 2026
Kind: B2

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Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the first memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.

Claims (86)

1 . A memory device comprising:

a first memory cell array;

a second memory cell array arranged above the first memory cell array in a first direction;

a third memory cell array arranged adjacent to the first memory cell array in a second direction intersecting with the first direction;

a fourth memory cell array arranged above the third memory cell array in the first direction and arranged adjacent to the second memory cell array in the second direction;

a first bit line coupled to the first memory cell array and the fourth memory cell array; and

a second bit line coupled to the second memory cell array and the third memory cell array.

2 . The memory device of claim 1 , further comprising:

a control chip comprising

a first sense amplifier coupled to the first memory cell array and the fourth memory cell array through the first bit line, and

a second sense amplifier coupled to the second memory cell array and the third memory cell array through the second bit line.

3 . The memory device of claim 2 ,

wherein the first memory cell array is arranged above the first sense amplifier in the first direction, and

wherein the third memory cell array is arranged above the second sense amplifier in the first direction.

4 . The memory device of claim 1 ,

wherein the first memory cell array includes a first memory cell coupled to a first word line,

wherein the second memory cell array includes a second memory cell coupled to the first word line,

wherein the third memory cell array includes a third memory cell coupled to a second word line, and

wherein the fourth memory cell array includes a fourth memory cell coupled to the second word line.

5 . The memory device of claim 4 ,

wherein the first memory cell array includes a first semiconductor structure extending in the first direction, the first memory cell is formed on the first semiconductor structure, and the first semiconductor structure is coupled to the first bit line,

wherein the second memory cell array includes a second semiconductor structure extending in the first direction, the second memory cell is formed on the second semiconductor structure, and the second semiconductor structure is coupled to the second bit line,

wherein the third memory cell array includes a third semiconductor structure extending in the first direction, the third memory cell is formed on the third semiconductor structure, and the third semiconductor structure is coupled to the second bit line, and

wherein the fourth memory cell array includes a fourth semiconductor structure extending in the first direction, the fourth memory cell is formed on the fourth semiconductor structure, and the fourth semiconductor structure coupled to the first bit line.

6 . The memory device of claim 1 , further comprising:

a first sense amplifier coupled to the first memory cell array and the fourth memory cell array through the first bit line, the first memory cell array being arranged above the first sense amplifier in the first direction; and

a second sense amplifier coupled to the second memory cell array and the third memory cell array through the second bit line, the third memory cell array being arranged above the second sense amplifier in the first direction.

7 . The memory device of claim 1 , further comprising:

a first memory chip comprising the first memory cell array and the third memory cell array; and

a second memory chip comprising the second memory cell array and the fourth memory cell array.

8 . The memory device of claim 7 , wherein the second memory chip comprises:

a first pad arranged on a surface of the second memory chip, the first pad being coupled to the fourth memory cell array through a portion of the first bit line, and

a second pad arranged on the surface of the second memory chip, the second pad being coupled to the second memory cell array through a portion of the second bit line, the second pad being closer to the fourth memory cell array than the second memory cell array, the first pad being closer to the second memory cell array than the fourth memory cell array.

9 . The memory device of claim 8 , wherein the first memory chip comprises:

a third pad arranged on a surface of the first memory chip, the third pad being coupled to the first pad, the third pad being coupled to the first memory cell array through another portion of the first bit line, and

a fourth pad arranged on the surface of the first memory chip, the fourth pad being coupled to the second pad, the fourth pad being coupled to the third memory cell array through another portion of the second bit line.

10 . The memory device of claim 9 ,

wherein the third pad is closer to the first memory cell array than the third memory cell array, and

wherein the fourth pad is closer to the third memory cell array than the first memory cell array.

11 . A memory device comprising:

a memory chip comprising:

a first memory cell array,

a second memory cell array arranged adjacent to the first memory cell array in a first direction,

a first pad arranged on a surface of the memory chip,

a second pad arranged on the surface of the memory chip, the second pad being closer to the second memory cell array than the first memory cell array, the first pad being closer to the first memory cell array than the second memory cell array,

a portion of a first bit line coupled to the first memory cell array and the second pad, and

a portion of a second bit line coupled to the second memory cell array and the first pad.

12 . The memory device of claim 11 , further comprising:

another memory chip arranged above the memory chip in a second direction intersecting with the first direction, the another memory chip comprising:

a third memory cell array,

a fourth memory cell array arranged adjacent to the third memory cell array in the first direction,

a third pad arranged on a surface of the another memory chip, the third pad being coupled to the first pad,

a fourth pad arranged on the surface of the another memory chip, the fourth pad being coupled to the second pad,

another portion of the second bit line coupled to the third memory cell array and the third pad, and

another portion of the first bit line coupled to the fourth memory cell array and the fourth pad.

13 . The memory device of claim 12 ,

wherein the third pad is closer to the third memory cell array than the fourth memory cell array, and

wherein the fourth pad is closer to the fourth memory cell array than the third memory cell array.

14 . The memory device of claim 12 ,

wherein the third memory cell array is arranged above the first memory cell array in the second direction, and

wherein the fourth memory cell array is arranged above the second memory cell array in the second direction.

15 . The memory device of claim 12 , wherein the another memory chip comprises:

a fifth pad arranged on another surface of the another memory chip facing away from the surface of the another memory chip, the fifth pad being coupled to the another portion of the second bit line, and

a sixth pad arranged on the another surface of the another memory chip, the sixth pad being coupled to the another portion of the first bit line.

16 . The memory device of claim 15 , further comprising:

a circuit chip arranged above the another memory chip in the second direction, the circuit chip comprising:

a seventh pad arranged on a surface of the circuit chip, the seventh pad being coupled to the fifth pad,

an eighth pad arranged on the surface of the circuit chip, the eighth pad being coupled to the sixth pad,

a first sense amplifier coupled to the seventh pad, and

a second sense amplifier coupled to the eighth pad.

17 . The memory device of claim 16 ,

wherein the first sense amplifier is arranged above the third memory cell array in the second direction, and

wherein the second sense amplifier is arranged above the fourth memory cell array in the second direction.

18 . A memory device comprising:

a first memory cell array;

a second memory cell array arranged above the first memory cell array in a first direction;

a third memory cell array arranged adjacent to the first memory cell array in a second direction intersecting with the first direction;

a fourth memory cell array arranged above the third memory cell array in the first direction and arranged adjacent to the second memory cell array in the second direction;

a first sense amplifier coupled to the first memory cell array and the fourth memory cell array, the first memory cell array arranged above the first sense amplifier in the first direction; and

a second sense amplifier coupled to the second memory cell array and the third memory cell array, the third memory cell array being arranged above the second sense amplifier in the first direction.

19 . The memory device of claim 18 , further comprising:

a first word line coupled to a gate of a first memory cell of the first memory cell array and a gate of a second memory cell of the second memory cell array; and

a second word line coupled to a gate of a third memory cell of the third memory cell array and a gate of a fourth memory cell of the fourth memory cell array.

20 . The memory device of claim 19 ,

wherein a voltage is applied to the first word line, while (i) the first sense amplifier performs an operation on the first memory cell of the first memory cell array through the first bit line and (ii) the second sense amplifier performs an operation on the second memory cell of the second memory cell array through the second bit line, and

wherein the voltage is applied to the second word line, while (i) the first sense amplifier performs an operation on the fourth memory cell of the fourth memory cell array through the first bit line and (ii) the second sense amplifier performs an operation on the third memory cell of the third memory cell array through the second bit line.