IP Library Granted Patent US 12,670,958
Granted Patent B2
US 12,670,958 · App. 18/388,930 · Granted Jun 30, 2026

Execution of prologue sub-operations of a programming operation during data loading

Inventors: Hojung Yun (San Jose, CA); Xiaoxiao Zhang (San Jose, CA); Yizhou Zhu (Fremont, CA); Dheeraj Srinivasan (San Jose, CA)
Assignee: Micron Technology, Inc.
G11C16/10G01N3/06G01N3/12G06F9/44521G01N2203/0017G01N2203/0411
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Quick Facts
Patent No.
US 12,670,958
App. No.
18/388,930
Granted
Jun 30, 2026
Kind
B2
Abstract

A request to execute a programming operation to program a set of memory cells of the memory array is identified, where the programming operation comprises a set of prologue sub-operations and a set of program sub-operations. A loading process is caused to be executed to load data associated with the programming operation to the memory device. During the loading process, at least a portion of the prologue sub-operations associated with the programming operation are caused to be executed. Following completion of the loading process, the set of program sub-operations of the programming operation are caused to be executed.

Claims (45)

1 . A memory device comprising:

a memory array; and

control logic, operatively coupled with the memory array, to perform operations comprising:

identifying a request to execute a programming operation to program a set of memory cells of the memory array, wherein the programming operation comprises a set of prologue sub-operations and a set of program sub-operations;

causing execution of a loading process to load data associated with the programming operation to the memory device;

causing execution of at least a portion of the set of prologue sub-operations associated with the programming operation, wherein the at least the portion of the set of prologue sub-operations and the loading process are executed concurrently; and

following completion of the loading process, causing execution of the set of program sub-operations of the programming operation.

2 . The memory device of claim 1 , wherein the at least the portion of the set of prologue sub-operations executed during the loading process comprises a first portion of the set of prologue sub-operations.

3 . The memory device of claim 2 , the operations further comprising:

following completion of the loading process, causing execution of a second portion of the set of prologue sub-operations.

4 . The memory device of claim 2 , the operations further comprising:

identifying the first portion of the set of prologue sub-operations executed during the loading process; and

based on the identifying, determining a remaining portion of the set of prologue sub-operations; and

following completion of the loading process, causing execution of the remaining portion of the set of prologue sub-operations prior to causing execution of the set of program sub-operations.

5 . The memory device of claim 1 , the operations further comprising:

sensing a voltage level associated with the set of memory cells to confirm completion of the programming operation.

6 . The memory device of claim 1 , wherein the set of prologue sub-operations comprises one or more of a variable initialization sub-operation, a temperature sensor initialization sub-operation, or a page buffer initialization sub-operation.

7 . The memory device of claim 1 , wherein the set of program sub-operations comprises one or more of applying one or more programming pulses, one or more program verify sub-operations, or a voltage discharge sub-operation.

8 . A method comprising:

identifying, by a processing device, a request to execute a programming operation to program a set of memory cells of a memory device, wherein the programming operation comprises a set of prologue sub-operations and a set of program sub-operations;

causing execution of a loading process to load data associated with the programming operation to the memory device;

causing execution of at least a portion of the set of prologue sub-operations associated with the programming operation, wherein the at least the portion of the set of prologue sub-operations and the loading process are executed concurrently; and

following completion of the loading process, causing execution of the set of program sub-operations of the programming operation.

9 . The method of claim 8 , wherein the at least the portion of the set of prologue sub-operations executed during the loading process comprises a first portion of the set of prologue sub-operations.

10 . The method of claim 9 , further comprising following completion of the loading process, causing execution of a second portion of the set of prologue sub-operations.

11 . The method of claim 9 , further comprising:

identifying the first portion of the set of prologue sub-operations executed during the loading process;

based on the identifying, determining a remaining portion of the set of prologue sub-operations; and

following completion of the loading process, causing execution of the remaining portion of the set of prologue sub-operations prior to causing execution of the set of program sub-operations.

12 . The method of claim 11 , further comprising sensing a voltage level associated with the set of memory cells to confirm completion of the programming operation.

13 . The method of claim 8 , wherein the set of prologue sub-operations comprises one or more of a variable initialization sub-operation, a temperature sensor initialization sub-operation, or a page buffer initialization sub-operation.

14 . The method of claim 8 , wherein the set of program sub-operations comprises one or more of applying one or more programming pulses, one or more program verify sub-operations, or a voltage discharge sub-operation.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

identifying a request to execute a programming operation to program a set of memory cells of a memory device, wherein the programming operation comprises a set of prologue sub-operations and a set of program sub-operations;

causing execution of a loading process to load data associated with the programming operation to the memory device;

causing execution of at least a portion of the set of prologue sub-operations associated with the programming operation, wherein the at least the portion of the set of prologue sub-operations and the loading process are executed concurrently; and

following completion of the loading process, causing execution of the set of program sub-operations of the programming operation.

16 . The non-transitory computer-readable storage medium of claim 15 , the operations further comprising sensing a voltage level associated with the set of memory cells to confirm completion of the programming operation.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein the at least the portion of the set of prologue sub-operations executed during the loading process comprises a first portion of the set of prologue sub-operations.

18 . The non-transitory computer-readable storage medium of claim 17 , the operations further comprising following completion of the loading process, causing execution of a second portion of the set of prologue sub-operations.

19 . The non-transitory computer-readable storage medium of claim 17 , the operations further comprising:

identifying the first portion of the set of prologue sub-operations executed during the loading process;

based on the identifying, determining a remaining portion of the set of prologue sub-operations; and

following completion of the loading process, causing execution of the remaining portion of the set of prologue sub-operations prior to causing execution of the set of program sub-operations.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein the set of prologue sub-operations comprises one or more of a variable initialization sub-operation, a temperature sensor initialization sub-operation, or a page buffer initialization sub-operation; and wherein the set of program sub-operations comprises one or more of applying one or more programming pulses, one or more program verify sub-operations, or a voltage discharge sub-operation.