Three-dimensional one time programmable memory

1 . A memory array comprising:

a first set of one-time programmable (OTP) cells connected between a first program control line and a first bit line, wherein each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first bit line, wherein the first program control line extends towards a first side of the memory array along a first direction, wherein the first bit line extends along the first direction towards a second side of the memory array facing away from the first side of the memory array, and wherein each switch of the first set of OTP cells includes a gate electrode coupled to a corresponding read control line extending along a second direction that is perpendicular to the first direction.

2 . The memory array of claim 1 , further comprising:

a second set of OTP cells connected between a second program control line and a second bit line, wherein each OTP cell of the second set of OTP cells includes a programmable storage device and a switch connected between the second program control line and the second bit line, wherein the second program control line extends towards the first side of the memory array, and wherein the second bit line extends towards the second side of the memory array.

3 . The memory array of claim 2 , wherein each switch of the first set of OTP cells includes the gate electrode coupled to a gate electrode of a corresponding switch of the second set of OTP cells through the corresponding read control line.

4 . The memory array of claim 1 , wherein each programmable storage device of the first set of OTP cells is a first transistor including a gate electrode connected to the first program control line.

5 . The memory array of claim 4 , wherein each switch of the first set of OTP cells is a second transistor including a source electrode connected to the first bit line.

6 . The memory array of claim 5 , wherein the first transistor is a first type of transistor.

7 . The memory array of claim 6 , wherein the second transistor includes a drain electrode coupled to the first transistor.

8 . The memory array of claim 7 , wherein the first transistor and the second transistor are same type of transistors.

9 . The memory array of claim 1 , wherein each programmable storage device of the first set of OTP cells includes a floating electrode.

10 . The memory array of claim 1 , wherein the first set of OTP cells is arranged in AND configuration.

11 . The memory array of claim 2 , wherein the second set of OTP cells is arranged in AND configuration.

12 . A memory array comprising:

a first set of one-time programmable (OTP) cells connected between a first program control line and a first bit line, wherein each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first bit line, wherein the first program control line extends towards a first side of the memory array along a first direction, and wherein the first bit line extends along the first direction towards a second side of the memory array facing away from the first side of the memory array; and

a second set of OTP cells connected between a second program control line and a second bit line, wherein each OTP cell of the second set of OTP cells includes a programmable storage device and a switch connected between the second program control line and the second bit line, wherein the second program control line extends towards the first side of the memory array, and wherein the second bit line extends towards the second side of the memory array;

wherein each switch of the first set of OTP cells includes a gate electrode coupled to a gate electrode of a corresponding switch of the second set of OTP cells through a corresponding read control line extending along a second direction that is perpendicular to the first direction.

13 . The memory array of claim 12 ,

wherein each programmable storage device of the first set of OTP cells is a first transistor including a gate electrode connected to the first program control line; and

wherein each switch of the first set of OTP cells is a second transistor including a source electrode connected to the first bit line.

14 . The memory array of claim 13 , wherein the first transistor is a first type of transistor.

15 . The memory array of claim 14 , wherein the second transistor includes a drain electrode coupled to the first transistor.

16 . The memory array of claim 15 , wherein the first transistor and the second transistor are same type of transistors.

17 . The memory array of claim 13 , wherein each programmable storage device of the first set of OTP cells includes a floating electrode.

18 . The memory array of claim 12 , wherein the first set of OTP cells is arranged in AND configuration.

19 . The memory array of claim 12 , wherein the second set of OTP cells is arranged in AND configuration.

20 . A memory array comprising:

a first set of one-time programmable (OTP) cells connected between a first program control line and a first bit line, wherein each OTP cell of the first set of OTP cells includes a programmable storage device and a switch connected between the first program control line and the first bit line, wherein the first program control line extends towards a first side of the memory array along a first direction, and wherein the first bit line extends along the first direction towards a second side of the memory array facing away from the first side of the memory array; and

a second set of OTP cells connected between a second program control line and a second bit line;

wherein each switch of the first set of OTP cells includes a gate electrode coupled to a gate electrode of a corresponding switch of the second set of OTP cells through a corresponding read control line extending along a second direction that is perpendicular to the first direction.