Device data path monitor

1 . An apparatus, comprising:

a device;

a processor coupled to the device and configured to:

determine whether the device is in an inactive state;

responsive to determining that the device is in the inactive state, alternate access of a number of addresses of the device by toggling between the number of addresses based on a clock signal, wherein memory cells of the device having the number of addresses store output data comprising predefined bit-value patterns;

monitor the output data, to monitor a read path of the device, generated by the device responsive to the number of addresses to determine whether accessing one or more of the number of addresses results in an error in the output data,

wherein the output data is provided by the device along a data path, and

wherein the output data is continuously monitored when the device is in the inactive state; and

perform an action responsive to determining that there is an error in the read path of the device based on the error in the output data.

2 . The apparatus of claim 1 , wherein the device is an addressable device.

3 . The apparatus of claim 2 , wherein the processor is further configured to provide an address to the addressable device.

4 . The apparatus of claim 3 , wherein the processor is configured to provide the output data to a checking circuitry.

5 . The apparatus of claim 4 , wherein the processor is configured to provide the output data to the checking circuitry via input/output (I/O) lines.

6 . The apparatus of claim 3 , wherein the processor configured to provide the address is further configured to provide one of a first address or a second address to the addressable device.

7 . The apparatus of claim 6 , wherein the processor is further configured to toggle between the first address or the second address, based on time, to select the address.

8 . The apparatus of claim 1 , wherein the processor is further configured to provide a functional address to the device responsive to determining that the device is active.

9 . A method, comprising:

monitoring whether a device is in an idle state based on a memory enable (ME) signal, wherein the ME signal having a first state corresponds to the device being in the idle state in which the device is not actively processing host read commands, and the ME signal having a second state corresponds to the device being in a non-idle state in which the device is configured to actively process host read commands;

responsive to the ME signal having the second state, read, from the device, data stored at a functional address corresponding to a received host read command;

responsive to the ME signal having the first state corresponding to the device being in the idle state, perform a read path monitor operation that includes:

selecting a first monitored address of a plurality of monitored addresses of the device to read;

reading monitored data stored at the first monitored address;

performing an error detection operation on the monitored data stored at the first monitored address to determine whether the monitored data has an error;

performing a reporting operation to report an error in a read path of the device responsive to detecting the error in the monitored data stored at the first monitored address; and

while the device remains in the idle state:

continuing to perform additional read operations by cycling through the plurality of monitored addresses.

10 . The method of claim 9 , wherein the idle state is a state in which the device receives the ME signal having the first state.

11 . The method of claim 9 , wherein the plurality of monitored addresses includes the first read address and a second read address, and further comprising providing one of the first read address or the second read address to the device.

12 . The method of claim 11 , wherein responsive to determining that the device is not write enabled or read enabled, providing the first address or the second address to the device repetitively over a period of time.

13 . The method of claim 9 , wherein the error is caused by timing errors.

14 . The method of claim 9 , wherein the error includes security errors.

15 . The method of claim 9 , wherein the error includes safety errors describing a safety of a system that includes the device.

16 . An apparatus, comprising:

a device;

a processor coupled to the device and configured to:

determine whether the device is inactive based on a memory enable (ME) signal, wherein the ME signal having a first state corresponds to the device being in the idle state in which the device is not actively processing host read commands, and the ME signal having a second state corresponds to the device being in a non-idle state in which the device is configured to actively process host read commands;

responsive to the ME signal having the second state, read, from the device, data stored at a functional address corresponding to a received host read command;

responsive to the ME signal having the first state corresponding to the device being in the idle state, perform a read path monitor operation that includes:

alternate providing a first address and a second address of a command utilizing a plurality of multiplexors (MUX), repetitively over a period of time and wherein memory cells of the device having the first address and the second address store monitored data comprising predefined bit-value patterns;

monitor the monitored data from the device generated responsive to receipt of the first address or the second address to determine whether there is an error associated with a data path of the device, wherein the monitored data comprises predefined bit-value patterns; and

perform an action responsive to determining that there is an error associated with the data path of the device.

17 . The apparatus of claim 16 , wherein the processor comprises the plurality of MUXs including a first MUX configured to provide the first address or the second address.

18 . The apparatus of claim 17 , wherein the plurality of MUXs includes a second MUX configured to provide one of the first address or the second address or the functional address to the device.

19 . The apparatus of claim 18 , wherein an output of the first MUX and the functional address are provided to the second MUX and wherein the second MUX provides the output of the first MUX or the functional address based on whether the device is idle.

20 . The apparatus of claim 16 , wherein the processor further comprises toggling circuitry to toggle between the first address and the second address repetitively over the period of time.