Thermistor integrated with a bias resistor
An electronic device including a thermistor and a bias reference resistor in a voltage divider configuration integrated into a single die and a method of fabricating the same. In an example, the electronic device comprises a substrate including an n-well region, a thermistor formed in the n-well region, and a bias resistor connected in series to the thermistor, the bias resistor formed in a region of the substrate isolated from the n-well region.
1 . An electronic device, comprising:
a substrate including an n-well region;
a thermistor formed in the n-well region; and
a bias resistor connected in series to the thermistor, the bias resistor formed in a region of the substrate isolated from the n-well region.
2 . The electronic device as recited in claim 1 , wherein the thermistor comprises a well resistor in the n-well region having a dopant species comprising at least one of phosphorous and arsenic.
3 . The electronic device as recited in claim 1 , wherein the bias resistor comprises a boron-doped polysilicon structure disposed over field oxide extending into the substrate.
4 . The electronic device as recited in claim 1 , further comprising a first plurality of fuses for tuning the thermistor and a second plurality of fuses for tuning the bias resistor.
5 . The electronic device as recited in claim 4 , wherein the first plurality of fuses for tuning the thermistor comprises a first subset of fuses spaced apart with a first pitch coupled to a first terminal of the thermistor and a second subset of fuses spaced apart with a second pitch greater than the first pitch and coupled to a second terminal of the thermistor.
6 . The electronic device as recited in claim 4 , wherein the second plurality of fuses for tuning the bias resistor comprises a first subset of fuses spaced apart with a first pitch coupled to a first terminal of the bias resistor and a second subset of fuses spaced apart with a second pitch greater than the first pitch and coupled to a second terminal of the bias resistor.
7 . The electronic device as recited in claim 1 , wherein the thermistor has a positive temperature coefficient.
8 . The electronic device as recited in claim 1 , wherein the thermistor has a negative temperature coefficient.
9 . The electronic device as recited in claim 1 , wherein the n-well region extends into an epitaxial layer of the substrate.
10 . The electronic device as recited in claim 1 , wherein the bias resistor and the thermistor are disposed relative to each other in a stack having a dielectric layer formed therebetween.
11 . A method of fabricating an electronic device, comprising:
forming voltage divider over a semiconductor substrate, including:
forming a thermistor in an n-well region extending into the semiconductor substrate;
forming a bias resistor over a region of the semiconductor substrate conductively isolated from the n-well region; and
connecting the thermistor and the bias resistor in series between a first reference voltage rail of the electronic device and a second reference voltage rail of the electronic device.
12 . The method as recited in claim 11 , wherein the thermistor comprises a well resistor in the n-well region having a dopant species comprising at least one of phosphorous and arsenic.
13 . The method as recited in claim 11 , wherein the bias resistor comprises a boron-doped polysilicon structure disposed over a field oxide extending into the semiconductor substrate.
14 . The method as recited in claim 11 , further comprising forming a first plurality of fuses over the semiconductor substrate for tuning the thermistor and a second plurality of fuses for tuning the bias resistor.
15 . An integrated circuit, comprising:
a semiconductor substrate die;
a field dielectric layer on the substrate die;
an n-well region in the substrate die;
a first resistor including a polysilicon body formed on the field dielectric layer;
a second resistor formed in the n-well region; and
conductive interconnections that connect the first resistor and the second resistor in series between a first terminal and a second terminal.
16 . The integrated circuit as recited in claim 15 , further comprising a third terminal connected to a conductive circuit node between the first and second resistors.
17 . The integrated circuit as recited in claim 16 , further comprising a first fuse bank connected in a circuit path between the third terminal and the first resistor and a second fuse bank connected in a circuit path between the third terminal and the second resistor.
18 . The integrated circuit as recited in claim 17 , further comprising a third fuse bank connected in a circuit path between the first terminal and the first resistor and a fourth fuse bank connected in a circuit path between the second terminal and the second resistor.
19 . The integrated circuit as recited in claim 15 , wherein the first resistor has a first temperature coefficient of resistance (TCR) and the second resistor has a lesser second TCR.
20 . The integrated circuit as recited in claim 19 wherein the second TCR is in a range of ±100 ppm/° C.