Reflective phase shifter for use in phased arrays

1 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal,

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) at least one sub-circuit having at least one binary switched phase bit, wherein the at least one sub-circuit is configured as a transmission line circuit, wherein a transmission line of the transmission line circuit terminates in an open circuit and a switch is shunted to ground along a length thereof, and wherein when in a conducting state, the transmission line is shorted with a reduced effective length, and when in an isolating state, the connection to ground is blocked and the open termination and full length of the transmission line determines an impedance of the device.

2 . The system of claim 1 , wherein the device comprises one to N switchable parallel phase bits, wherein each bit is switchable between two states, and wherein the reflection from the circuit can take on 2 N unique phase states, which are widely distributed from 0-360°.

3 . The system of claim 2 , wherein the value of N spans 3-8 switchable phase bits.

4 . The system of claim 1 , wherein the system is configured for use with radio frequency waves, acoustic domains, or optical domains.

5 . The system of claim 1 , wherein the system is configured for use with an integrated circuit.

6 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal,

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) at least one sub-circuit having at least one binary switched phase bit, wherein the at least one sub-circuit is configured as a transmission line circuit, wherein the transmission line circuit terminates in a short circuit, and wherein the transmission line circuit is segmented into two sections by a series switch.

7 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal,

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) at least one sub-circuit having at least one binary switched phase bit, wherein the at least one sub-circuit is configured as a transmission line circuit, wherein a first transmission line of the transmission line circuit is connected to a common input, wherein a second transmission line of the transmission line circuit is isolated, wherein one of the first and second transmission lines is terminated in a short circuit, and wherein the other transmission line is terminated in an open circuit.

8 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal,

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) at least one sub-circuit having at least one binary switched phase bit, wherein the at least one sub-circuit is configured as a transmission line circuit, wherein a transmission line of the transmission line circuit terminates in a short circuit, and wherein along a length of the transmission line a switch shunts to ground.

9 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) at least one sub-circuit having at least one binary switched phase bit, wherein the at least one sub-circuit is configured as a transmission line circuit, wherein a transmission line of the transmission line circuit terminates in an open circuit, and wherein the transmission line is segmented into two sections by a series switch.

10 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal,

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the device; and

(b) wherein the at least one phase bits are configured such that in at least one state inputs of all of the plurality of phase bits are DC-coupled to ground, and in at least one other state inputs of all of the plurality of phase bits are a DC high impedance or open circuit.

11 . A system, comprising:

(a) a device including a circuit configured to produce a phase shift in a reflected signal

(i) wherein a plurality of phase bits are situated in parallel relative to one another within the device,

(ii) wherein each phase bit operates on a fraction of incident signal power, and

(iii) wherein reflections from all parallel phase bits are recombined into a single signal reflected from the phase shifting device; and

(b) wherein the device includes a set of parallel sub-circuit bits, wherein a subset of bits of the set of parallel sub-circuit bits is operated at a first frequency (f1), and another subset of bits of the set of parallel sub-circuit bits operates a second frequency (f2), and wherein individual bits of the set of parallel sub-circuit bits may be shared across multiple subsets, and any number of subsets or bits of the set of parallel sub-circuit bits can be implemented.