IP Library Granted Patent US 12671316
Granted Patent B2
US 12671316 · App. 18/602,432 · Granted Jun 30, 2026

Built-in ripple injection circuit and control chip

Inventors: Rulong Jiang (Shanghai, CN); Zhen Zhu (Shanghai, CN); Xiaoru Gao (Shanghai, CN); Yi Zhang (Shanghai, CN); Ge Yang (Shanghai, CN)
Assignee: SHANGHAI BRIGHT POWER SEMICONDUCTOR CO., LTD.
H02M1/143H02M3/156H03F3/45475H03F3/456
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12671316
App. No.
18/602,432
Granted
Jun 30, 2026
Kind
B2
Abstract

The present invention provides a built-in ripple injection circuit and a control chip, in which a divided feedback voltage is obtained by division of an output voltage by a feedback circuit, and high-frequency ripple in the output voltage is obtained by an operational amplifier and a first capacitor. Moreover, the high-frequency ripple is injected at a third terminal of a source follower. As a result, the feedback voltage is a superimposition of the divided feedback voltage with the high-frequency ripple. This can enhance stability and interference resilience of a power supply system operating in a ripple-based COT control mode. Further, the built-in ripple circuit can be integrated in the control chip. This dispenses with the use of a large capacitor and satisfactorily addresses applications requiring on-chip integration of the feedback circuit, reducing the cost of the power supply system.

Claims (15)

1 . A control chip, comprising an built-in ripple injection circuit integrated within the control chip and comprising:

a feedback circuit comprising: a first terminal for receiving an output voltage; a grounded second terminal; and an output terminal for outputting a divided feedback voltage;

an operational amplifier comprising a first input terminal, which is connected to the output terminal of the feedback circuit and configured to receive the divided feedback voltage;

a first capacitor comprising: a first terminal connected to the first terminal of the feedback circuit; and a second terminal, which is connected to an output terminal of the operational amplifier and configured to couple high-frequency ripple in the output voltage to the output terminal of the operational amplifier; and

a source follower comprising: a first terminal connected to the output terminal of the operational amplifier; a second terminal connected to the first terminal of the first capacitor; and a third terminal, which is connected to a second input terminal of the operational amplifier and configured to output a feedback voltage, and

the control chip further comprising another operational amplifier,

the other operational amplifier comprising: a first input terminal for receiving a reference voltage; a second input terminal, which is coupled to the third terminal of the source follower and configured to receive the feedback voltage; and an output terminal for outputting a control signal.

2 . The control chip of claim 1 , further comprising a second capacitor, the second capacitor comprising: a first terminal connected to the output terminal of the operational amplifier; and a grounded second terminal.

3 . The control chip of claim 2 , wherein a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor is between 1:5 and 5:1.

4 . The control chip of claim 1 , wherein the operational amplifier is an operational transconductance amplifier and a gain of the operational transconductance amplifier is between 10 nS and 250 nS.

5 . The control chip of claim 4 , wherein the gain of the operational transconductance amplifier is positively correlated with a capacitance of the first capacitor.

6 . The control chip of claim 5 , wherein a ratio of the gain of the operational transconductance amplifier to the capacitance of the first capacitor is between 5 nS/pF and 30 nS/pF.

7 . The control chip of claim 1 , wherein the feedback circuit comprises a first resistor and a second resistor, a first terminal of the first resistor connected to the first terminal of the feedback circuit, a second terminal of the first resistor and a first terminal of the second resistor both connected to the output terminal of the feedback circuit, a second terminal of the second resistor connected to the second terminal of the feedback circuit.

8 . The control chip of claim 1 , further comprising a current source, the current source comprising: a first terminal connected to the third terminal of the source follower; and a grounded second terminal.

9 . The control chip of claim 1 , wherein the operational amplifier is a folded cascode amplifier, and a negative feedback is provided at a source of the operational amplifier.