IP Library Granted Patent US 12671335
Granted Patent B2
US 12671335 · App. 18/673,633 · Granted Jun 30, 2026

Comparator with noise cancellation for switching power converters

Inventors: Yash Shah (Mumbai, IN); Dattatreya Baragur Suryanarayana (Bangalore-Bagmane Lakeview, IN); Bikash Pradhan (Bangalore-Bagmane Lakeview, IN); Mayank Jain (Kodihalli Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H02M3/158H03K5/2481
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Quick Facts
Patent No.
US 12671335
App. No.
18/673,633
Granted
Jun 30, 2026
Kind
B2
Abstract

Comparator circuitry for power converters. In an example, a circuit includes a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal. The circuit further includes a first transistor coupled between a boot terminal and the first comparator input and having a control terminal coupled to a switching terminal, and a second transistor coupled between the boot terminal and the second comparator input and having a control terminal coupled to the switching terminal. Also, a third transistor is coupled between the supply terminal and the second comparator input, and a voltage reference generator is coupled to the supply terminal and to a control terminal of the third transistor.

Claims (59)

1 . A circuit comprising:

a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal;

a first transistor coupled between a boot terminal and the first comparator input, and having a control terminal coupled to a switching terminal;

a second transistor coupled between the boot terminal and the second comparator input, and having a control terminal coupled to the switching terminal;

a third transistor coupled between the supply terminal and the second comparator input; and

a voltage reference generator coupled to the supply terminal and to a control terminal of the third transistor.

2 . The circuit of claim 1 , wherein the first, second, and third transistors are drain extended p-channel field effect transistors.

3 . The circuit of claim 1 , further comprising:

a first resistor coupled between the boot terminal and the first transistor, the first resistor having a first resistance value;

a second resistor coupled between the boot terminal and the second transistor, wherein the second resistor has a second resistance value that is substantially N times the first resistance value, wherein N is a positive value; and

a third resistor coupled between the supply terminal and the third transistor, the third resistor having substantially the first resistance value.

4 . The circuit of claim 3 , further comprising:

a fourth resistor coupled between the first transistor and a ground terminal; and

a fifth resistor coupled between the second comparator input and the ground terminal, the fifth resistor having a substantially same resistance value as the fourth resistor.

5 . The circuit of claim 3 , further comprising:

a fourth resistor coupled between the supply terminal and the control terminal of the third transistor.

6 . The circuit of claim 5 , wherein the voltage reference generator is configured to generate a threshold voltage across the fourth resistor; and

wherein the comparator is configured to provide an output signal at the comparator output, the output signal transitioning from a first value to a second value responsive to a difference between a boot voltage at the boot terminal and a switching voltage at the switching terminal transgressing the threshold voltage.

7 . The circuit of claim 3 , further comprising:

a capacitor coupled between the boot terminal and the switching terminal.

8 . A circuit comprising:

a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal;

first circuitry coupled to a boot terminal and to a switching terminal, the first circuitry configured to produce, at the first comparator input, a first voltage signal proportional to a difference between a boot voltage at the boot terminal and a switching voltage at the switching terminal, the first voltage signal including a first noise component;

second circuitry coupled to the supply terminal and configured to produce, at the second comparator input, a second voltage signal; and

noise cancellation circuitry coupled to the boot terminal, the switching terminal, and the second circuitry, the noise cancellation circuitry configured to introduce into the second voltage signal a second noise component substantially matching the first noise component;

wherein the comparator is configured to produce, at the comparator output, an output signal that transitions from a first value to a second value responsive to the first voltage signal transgressing a threshold value based on the second voltage signal.

9 . The circuit of claim 8 , wherein the first circuitry comprises a first resistor coupled between the first comparator input and a ground terminal, and wherein the first circuitry is configured to convert a voltage difference between the boot voltage and switching voltage to a current that flows through the first resistor to produce the first voltage signal;

wherein the second circuitry comprises a second resistor coupled between the second comparator input and the ground terminal, the second resistor having a substantially same resistance value as the first resistor.

10 . The circuit of claim 9 , wherein the second circuitry comprises a voltage reference generator coupled to the supply terminal and configured to produce a threshold voltage having the threshold value; and wherein the second voltage signal is based on the threshold voltage.

11 . The circuit of claim 10 , wherein the first circuitry further comprises:

a third resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the boot terminal; and

a first transistor coupled between the second resistor terminal and the first comparator input, and having a control terminal coupled to the switching terminal.

12 . The circuit of claim 11 , wherein the second circuitry further comprises:

a fourth resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the supply terminal, the fourth resistor having a substantially same resistance value as the third resistor; and

a second transistor coupled between the fourth resistor terminal and the second comparator input, and having a control terminal coupled to the voltage reference generator.

13 . The circuit of claim 12 , wherein the second circuitry comprises a fifth resistor coupled between the supply terminal and the control terminal of the second transistor; wherein the voltage reference generator is configured to produce the threshold voltage across the fifth resistor.

14 . The circuit of claim 12 , wherein the noise cancellation circuitry comprises:

a fifth resistor having a fifth resistor terminal and a sixth resistor terminal, the fifth resistor terminal coupled to the boot terminal, the fifth resistor having a resistance value that is substantially N times a resistance value of the third resistor, wherein N is a positive value; and

a third transistor coupled between the sixth resistor terminal and the second comparator input, and having a control terminal coupled to the switching terminal.

15 . The circuit of claim 14 , wherein the first, second, and third transistors are drain extended p-channel field effect transistors.

16 . The circuit of claim 9 , wherein the first circuitry comprises a first capacitor coupled in parallel with the first resistor; and

wherein the second circuitry comprises a second capacitor coupled in parallel with the second resistor, the second capacitor having a substantially same capacitance value as the first capacitor.

17 . A buck converter comprising:

a first transistor coupled between an input voltage terminal and a switching terminal;

a second transistor coupled between the switching terminal and a ground terminal;

a driver coupled to a boot terminal and the switching terminal, and having a driver output coupled to a control terminal of the first transistor, the driver configured to provide a drive signal at the control terminal of the first transistor; and

a boot comparator system configured to monitor a boot voltage at the boot terminal, the boot comparator system including

a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal,

a third transistor coupled between the boot terminal and the first comparator input, and having a control terminal coupled to the switching terminal,

a fourth transistor coupled between the boot terminal and the second comparator input, and having a control terminal coupled to the switching terminal,

a fifth transistor coupled between the supply terminal and the second comparator input, and

a voltage reference generator coupled to the supply terminal and to a control terminal of the fifth transistor.

18 . The buck converter of claim 17 , wherein the third, fourth, and fifth transistors are drain extended p-channel field effect transistors; and wherein the first transistor is an n-channel field effect transistor.

19 . The buck converter of claim 17 , wherein the boot comparator system further comprises:

a first resistor coupled between the third transistor and a ground terminal;

a second resistor coupled between the second comparator input and the ground terminal, the second resistor having a substantially same resistance value as the first resistor; and

a third resistor coupled between the supply terminal and the control terminal of the fifth transistor.

20 . The buck converter of claim 19 , wherein the voltage reference generator is configured to generate a threshold voltage across the third resistor; and

wherein the comparator is configured to provide an output signal at the comparator output, the output signal transitioning from a first value to a second value responsive to a difference between the boot voltage and a switching voltage at the switching terminal transgressing the threshold voltage.