Amplitude modulation-phase modulation (AM-PM) linearization in a power amplifier using bias circuitry
Amplitude modulation-phase modulation (AM-PM) linearization in a power amplifier using bias circuitry, which fixes a bias of a cascode transistor within a power amplifier is disclosed. In particular, the cascode transistor may switch between operation in a saturation mode and a triode mode. The bias is set such that the cascode transistor operates at a fixed duty cycle in the triode mode relative to the saturation mode for a wide range of signal levels from small-signal to large-signal. An exemplary duty cycle is fifty percent (50%), although other duty cycles may be used. This bias will result in a constant capacitance contributed by the cascode device to the power amplifier over a wide signal level range.
1 . A power amplifier stage comprising: a cascode transistor comprising a gate; and a bias circuit coupled to the gate, the bias circuit configured to hold a voltage level at the gate equal to a drain voltage plus the device threshold voltage of the cascode transistor such that entry of the cascode transistor into the triode mode is controlled to a fixed duty cycle to maintain a constant average capacitance.
2 . The power amplifier stage of claim 1 , wherein the cascode transistor comprises a field effect transistor (FET).
3 . The power amplifier stage of claim 2 , further comprising a transconductance device and a middle cascode device, wherein the cascode transistor and the middle cascode device are cascodes relative to the transconductance device.
4 . The power amplifier stage of claim 2 , wherein the FET comprises an n-type FET (NFET).
5 . The power amplifier stage of claim 4 , wherein a gate voltage modified by the device threshold voltage comprises a drain voltage summed with the device threshold voltage.
6 . The power amplifier stage of claim 2 , wherein the FET comprises a p-type FET (PFET).
7 . The power amplifier stage of claim 6 , wherein a gate voltage modified by the device threshold voltage comprises the device threshold voltage subtracted from a drain voltage.
8 . The power amplifier stage of claim 2 implemented in a bulk complementary metal oxide semiconductor (CMOS) device.
9 . The power amplifier stage of claim 2 implemented in a silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) device.
10 . The power amplifier stage of claim 2 implemented in a silicon on sapphire (SOS) complementary metal oxide semiconductor (CMOS) device.
11 . The power amplifier stage of claim 1 , wherein the bias circuit is configured to operate the cascode transistor in a triode mode for a fixed duty cycle.
12 . The power amplifier stage of claim 11 , wherein the fixed duty cycle is 50%.
13 . The power amplifier stage of claim 1 , further comprising a second cascode transistor and wherein the bias circuit is configured to operate the cascode transistor in a triode mode for 50% of a radio frequency (RF) cycle and operate the second cascode transistor in the triode mode for another 50% of the RF cycle.
14 . The power amplifier stage of claim 3 , further comprising a drain-to-source parallel capacitance for the middle cascode device.
15 . A radio frequency (RF) circuit comprising:
a cascode power amplification stage comprising a cascode gate and an output node; a threshold voltage bias stage matched to the cascode power amplification stage and configured to keep the cascode gate within one threshold voltage from a direct current (DC) voltage level of the output node such that the cascode power amplification stage is at a verge of entering a triode operation; and a bias circuit configured to hold a voltage level at the gate equal to a drain voltage plus the device threshold voltage of the cascode transistor such that entry of the cascode transistor into the triode mode is controlled to a fixed duty cycle to maintain a constant average capacitance.
16 . The RF circuit of claim 15 , wherein the cascode power amplification stage stays in the triode operation for a fixed duty cycle for all signal levels.
17 . The RF circuit of claim 16 , wherein the fixed duty cycle is 50%.
18 . The RF circuit of claim 15 , wherein two cascode devices are alternatively operating in the triode operation.
19 . The RF circuit of claim 18 , wherein an n-type field effect transistor (FET) (NFET) is in the triode operation for 50% of an RF cycle and a p-type FET (PFET) is in the triode operation for the other 50% of the RF cycle.
20 . A power amplifier stage comprising:
a cascode transistor comprising a gate, a drain, and a source, the cascode transistor having a device threshold defined as a difference between a gate voltage and a drain voltage that causes the cascode transistor to enter a triode mode of operation from a saturation mode of operation; and
a bias circuit coupled to the gate, the bias circuit configured to hold a voltage level at the gate equal to a drain voltage plus the device threshold voltage of the cascode transistor such that entry of the cascode transistor into the triode mode is controlled to a fixed duty cycle to maintain a constant average capacitance.