IP Library › Granted Patent US 12671376

Granted Patent B2

US 12671376 · App. 18/243,597 · Granted Jun 30, 2026

Amplifier circuit and system

Inventors: Akira Yamauchi (Yokohama Kanagawa, JP); Hiroshi Yoshino (Yokohama Kanagawa, JP)

Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation

H03F3/45183 H03F1/0233 H03F3/45273 H03F2200/261

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Quick Facts

Patent No.: US 12671376
App. No.: 18/243,597
Granted: Jun 30, 2026
Kind: B2

External Links

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Abstract

A first circuit outputs first and second currents having different magnitudes. A second circuit receives the first current and first and second voltages, and outputs third and fourth currents based on the first and second voltages. A third circuit receives the second current and the first and second voltages, and outputs fifth and sixth currents based on the first and second voltages. A fourth circuit outputs an eighth current having a magnitude of the magnitude of the third current without a magnitude of a seventh current, which is a sum of the fifth and sixth currents, and a ninth current having a magnitude of the magnitude of the fourth current without the magnitude of the seventh current. A fifth circuit receives the eighth and ninth currents, outputs tenth and eleventh currents based on the eighth and ninth currents to a first end.

Claims (82)

1 . An amplifier circuit comprising:

a first circuit configured to output a first current and a second current, the second current having a magnitude difference from a magnitude of the first current;

a second circuit configured to receive the first current, to receive a first voltage and a second voltage, and to output a third current and a fourth current, the third current having a magnitude that is based on the first voltage and the second voltage, the fourth current having a magnitude that is based on the first voltage and the second voltage;

a third circuit configured to receive the second current, to receive the first voltage and the second voltage, and to output a fifth current and a sixth current, the fifth current having a magnitude that is based on the first voltage and the second voltage, the sixth current having a magnitude that is based on the first voltage and the second voltage;

a fourth circuit configured to output an eighth current and a ninth current, the eighth current having a magnitude obtained by subtracting a magnitude of a seventh current from the magnitude of the third current, the seventh current being a sum of the fifth current and the sixth current, the ninth current having a magnitude obtained by subtracting the magnitude of the seventh current from the magnitude of the fourth current; and

a fifth circuit configured to receive the eighth current and the ninth current, to output a tenth current to a first end, and to output an eleventh current to the first end, the tenth current being based on the eighth current, the eleventh current being based on the ninth current.

2 . The amplifier circuit according to claim 1 , wherein

the second circuit includes:

a first transistor including a second end that receives the first current, a third end that outputs the third current, and a first gate that receives the first voltage; and

a second transistor including a fourth end that receives the first current, a fifth end that outputs the fourth current, and a second gate that receives the second voltage, wherein

the third circuit includes:

a third transistor including a sixth end that receives the second current, a seventh end that outputs the fifth current, and a third gate that receives the first voltage; and

a fourth transistor including seventh end that receives the second current, an eighth end that outputs the sixth current, and a fourth gate that receives the second voltage.

3 . The amplifier circuit according to claim 2 , wherein

the first transistor and the second transistor have a substantially identical size, and

the third transistor and the fourth transistor have a substantially identical size.

4 . The amplifier circuit according to claim 2 , wherein

the first transistor, the second transistor, the third transistor, and the fourth transistor have a substantially identical current density.

5 . The amplifier circuit according to claim 2 , wherein

the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in proximity to one another.

6 . The amplifier circuit according to claim 2 , wherein

the fourth circuit includes a first current mirror circuit configured to receive the seventh current and to output a tenth current and an eleventh current,

the third current is a sum of the eighth current and the tenth current,

the fourth current is a sum of the ninth current and the eleventh current,

the fifth circuit includes:

a second current mirror circuit configured to receive the eighth current and to output the tenth current; and

a third current mirror circuit configured to receive the ninth current and to output a twelfth current, and

the first circuit includes a fifth current mirror circuit configured to receive a thirteenth current and to output the first current and the second current.

7 . The amplifier circuit according to claim 1 , wherein

the fourth circuit includes a first current mirror circuit configured to receive the seventh current and to output a tenth current and an eleventh current,

the third current is a sum of the eighth current and the tenth current, and

the fourth current is a sum of the ninth current and the eleventh current.

8 . The amplifier circuit according to claim 7 , wherein

the first current mirror circuit includes a fifth transistor, a sixth transistor, and a seventh transistor,

the fifth transistor includes a ninth end and a fifth gate, the ninth end being coupled to a third end that outputs the first current,

the sixth transistor includes a tenth end and a sixth gate, the tenth end being coupled to a fifth end that outputs the second current,

the seventh transistor includes an eleventh end and a seventh gate, the eleventh end being coupled to a first node that receives the fifth current and the sixth current, and

the seventh gate is coupled to the eleventh end, the fifth gate, and the sixth gate.

9 . The amplifier circuit according to claim 1 , wherein

the fifth circuit includes:

a second current mirror circuit configured to receive the eighth current and to output the tenth current; and

a third current mirror circuit configured to receive the ninth current and to output a twelfth current.

10 . The amplifier circuit according to claim 9 , wherein

the second current mirror circuit includes an eighth transistor and a ninth transistor,

the eighth transistor includes a twelfth end and a seventh gate, the twelfth end receiving the third current, the seventh gate being coupled to the twelfth end,

the ninth transistor includes a thirteenth end coupled to the first end and an eighth gate coupled to the seventh gate,

the third current mirror circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor,

the tenth transistor includes a fourteenth end and a ninth gate, the fourteenth end receiving the fourth current, the ninth gate being coupled to the fourteenth end,

the eleventh transistor includes a fifteenth end and a tenth gate, the tenth gate being coupled to the ninth gate,

the twelfth transistor includes a sixteenth end coupled to the fifteenth end and an eleventh end coupled to the sixteenth end, and

the thirteenth transistor includes a seventeenth end coupled to the first end and a twelfth gate coupled to the eleventh gate.

11 . The amplifier circuit according to claim 1 , wherein

the first circuit includes a fifth current mirror circuit configured to receive a thirteenth current and to output the first current and the second current.

12 . The amplifier circuit according to claim 11 , wherein

the fifth current mirror circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor,

the fourteenth transistor includes an eighteenth end and a thirteenth gate, the eighteenth end receiving the thirteenth current, the thirteenth gate being coupled to the eighteenth end,

the fifteenth transistor includes a nineteenth end and a fourteenth gate, the nineteenth end outputting the first current, the fourteenth gate being coupled to the thirteenth gate, and

the sixteenth transistor includes a twentieth end and a fifteenth gate, the twentieth end outputting the second current, the fifteenth gate being coupled to the thirteenth gate.

13 . The amplifier circuit according to claim 12 , wherein

the sixteenth transistor has a smaller size than a size of the fifteenth transistor.

14 . The amplifier circuit according to claim 13 , wherein

the sixteenth transistor has either a gate width smaller than a gate width of the fifteenth transistor or a gate length greater than a gate length of the fifteenth transistor.

15 . A system comprising:

a load;

the amplifier circuit according to claim 1 ; and