Process voltage temperature compensated current-starved inverter ring oscillator

1 . An apparatus, comprising:

a ring oscillator including:

a set of cascaded current-starved inverters arranged in a ring; and

a set of field effect transistors (FETs) coupled in series with the set of cascaded current-starved inverters between an upper voltage rail and a lower voltage rail, respectively;

a negative to absolute temperature (NTAT) current source configured to generate a NTAT current, the NTAT current source comprising

a constant current source configured to generate a substantially constant current towards a node, and

a positive to absolute temperature (PTAT) current source configured to generate a PTAT current from the node, wherein the node is situated between the constant current source and the one or more current mirrors, wherein the PTAT current source comprises

an enable circuit,

a startup circuit coupled to the enable circuit, and

a PTAT current generator coupled to the enable circuit and the startup circuit, the PTAT current generator comprising

a first p-channel field effect transistor (PFET) coupled in series with a diode-connected n-channel field effect transistor (NFET) between the upper voltage rail and the lower voltage rail, and

a diode-connected PFET, a first NFET, and a second NFET all coupled in series between the upper voltage rail and the lower voltage rail, wherein the diode-connected PFET and the first PFET include respective gates coupled together, and wherein the diode-connected NFET, the first NFET, and the second NFET include respective gates coupled together; and

one or more current mirrors coupling the NTAT current source to the set of FETs.

2 . The apparatus of claim 1 , wherein the PTAT current source is configured to change the PTAT current based on a control signal.

3 . The apparatus of claim 1 , wherein the PTAT current source is configured to generate a set of increasing PTAT currents including the PTAT current based on a control signal.

4 . The apparatus of claim 1 , wherein the PTAT current source is configured to cease generating the PTAT current source based on a control signal.

5 . The apparatus of claim 1 , wherein the enable circuit comprises:

a second PFET coupled in series with a third NFET between the upper voltage rail and the lower voltage rail, wherein the second PFET and the third NFET include respective gates configured to receive an enable control signal;

a third PFET including a source coupled to the upper voltage rail, a gate coupled to the gate of the second PFET, and a drain coupled to the gates of the diode-connected PFET and the first PFET of the PTAT current generator; and

a fourth NFET including a gate coupled to respective drains of the second PFET and the third NFET, a drain coupled to the respective gates of the diode-connected NFET, the first NFET, and the second NFET, and a source coupled to the lower voltage rail.

6 . The apparatus of claim 5 , wherein the startup circuit comprises a fourth PFET and a fifth PFET coupled in series between the gate of the diode-connected PFET and the gate of the diode-connected NFET, wherein the fourth PFET includes a gate coupled to the gate of the diode-connected NFET, wherein the fifth PFET includes a gate coupled to respective drains of the second PFET and the third NFET, and wherein the upper voltage rail is coupled to a drain of the fourth PFET and to a source of the fifth PFET.

7 . The apparatus of claim 1 , wherein the PTAT current source comprises a programmable current circuit coupled to the PTAT current generator.

8 . The apparatus of claim 7 , wherein the programmable current circuit comprises:

a first NFET coupled in series with a second NFET between the node and the lower voltage rail, wherein the first NFET includes a gate configured to receive a first bit of a program current control signal, and wherein the second NFET includes a gate coupled to the PTAT current generator; and

a third NFET coupled in series with a fourth NFET between the node and the lower voltage rail, wherein the third NFET includes a gate configured to receive a second bit of the program current control signal, and wherein the fourth NFET includes a gate coupled to the PTAT current generator.

9 . The apparatus of claim 1 , wherein the one or more current mirrors comprises a diode-connected FET coupled in series with the NTAT current source between the upper voltage rail and the lower voltage rail, wherein the diode-connected FET includes a gate coupled to respective gates of the set of FETs.

10 . The apparatus of claim 9 , wherein the FET and the set of FETs each comprises an n-channel field effect transistor (NFET).

11 . The apparatus of claim 1 , wherein the set of cascaded current-starved inverters are each configured to receive one or more control signals to control a frequency of a clock signal generated by the ring oscillator.

12 . The apparatus of claim 1 , further comprising an amplifier configured to generate a positive control signal and a negative control signal based on a frequency-control signal, wherein the positive and negative control signals are configured to control a current through each of the set of cascaded current-starved inverters.