Constant power active discharge of energy storage circuit
A circuit includes a reference signal generator, a comparator, a one-shot circuit, and a gate driver. The reference signal generator has an output terminal, a first input terminal configured to receive a discharge time select value, and a second input terminal configured to receive a stop voltage select value. The comparator has an output terminal, a first input terminal configured to receive a sensed voltage, and a second input terminal coupled to the output terminal of the reference signal generator. The one-shot circuit has an output terminal, a first input terminal coupled to the output terminal of the comparator, and a second input terminal configured to receive an on-time value. The gate driver has an output terminal, and an input terminal coupled to the output terminal of the one-shot circuit.
1 . A circuit, comprising:
a reference signal generator having first and second input terminals and an output terminal, the first input terminal of the reference signal generator configured to receive a discharge time select value indicating a discharge time, and the second input terminal of the reference signal generator configured to receive a stop voltage select value indicating a target voltage to discharge to within the discharge time;
a comparator having first and second input terminals, and an output terminal, the first input terminal of the comparator configured to receive a sensed voltage, and the second input terminal of the comparator coupled to the output terminal of the reference signal generator;
a one-shot circuit having first and second input terminals, and an output terminal, the first input terminal of the one-shot circuit coupled to the output terminal of the comparator, and the second input terminal of the one-shot circuit configured to receive an on-time value; and
a gate driver having an input terminal and an output terminal, the input terminal of the gate driver coupled to the output terminal of the one-shot circuit.
2 . The circuit of claim 1 , further comprising:
an AND logic circuit having first and second input terminals, and an output terminal, the first input terminal of the AND logic circuit coupled to the output terminal of the comparator, and the output terminal of the AND logic circuit coupled to the first input terminal of the one-shot circuit; and
a clock generator having an output terminal coupled to the second input terminal of the AND logic circuit.
3 . The circuit of claim 1 , further comprising a second comparator having first and second inputs, and an output terminal, the first input terminal of the second comparator coupled to the first input terminal of the comparator, the second input terminal configured to receive a fault reference signal formed by adding a fault offset level value to a reference signal provided by the reference signal generator, and the output terminal of the second comparator coupled to a second input terminal of the gate driver.
4 . The circuit of claim 1 , further comprising a voltage sense circuit having first and second terminals, and an output terminal, the second terminal of the voltage sense circuit coupled to a ground terminal, and the output terminal of the voltage sense circuit coupled to the first input terminal of the comparator.
5 . The circuit of claim 4 , wherein the voltage sense circuit comprises a voltage divider having an output coupled to the first input terminal of the comparator.
6 . The circuit of claim 4 , further comprising a capacitor having first and second terminals, the first terminal of the capacitor coupled to the first terminal of the voltage sense circuit, and the second terminal of the capacitor coupled to the ground terminal.
7 . The circuit of claim 4 , further comprising a transistor having first and second terminals, and having a control terminal, the first terminal of the transistor coupled to the first terminal of the voltage sense circuit, the second terminal of the transistor coupled to the ground terminal, and the control terminal of the transistor coupled to the output terminal of the gate driver.