Isolated communications lane demodulator
An envelope detector comprises a first differential transistor pair that receives first and second input signals, a second differential transistor pair that receives third and fourth input signals, a resistor, a current source, and a comparator. The first and second differential pairs each comprise two transistors having first current terminals coupled together and second current terminals coupled together. The resistor is coupled between the second current terminals of the first and second differential pairs. The current source has a first terminal coupled to the second terminal of the resistor and to second current terminals of the second differential pair and a second terminal configured to receive a negative supply voltage. The comparator has a negative input coupled to first current terminals of the first differential pair and a positive input coupled to first current terminals of the second differential pair.
1 . An apparatus, comprising:
an envelope detector having first differential inputs, second differential inputs, and a detector output, the envelope detector including:
a first transistor having a first control terminal, a first current terminal, and a second current terminal;
a second transistor having a second control terminal, a third current terminal, and a fourth current terminal, in which the third current terminal is coupled to the first current terminal, the fourth current terminal is coupled to the second current terminal, and the first and second control terminals coupled to the first differential inputs;
a first filter coupled between the first current terminal and a first supply voltage terminal;
a third transistor having a third control terminal, a fifth current terminal, and a sixth current terminal;
a fourth transistor having a fourth control terminal, a seventh current terminal, and an eighth current terminal, in which the seventh current terminal is coupled to the fifth current terminal, and the eighth current terminal is coupled to the sixth current terminal, and the third and fourth control terminals coupled to the second differential inputs;
a second filter coupled between the fifth current terminal and the first supply voltage terminal;
a current source coupled to a second supply voltage terminal;
a resistor coupled between second and fourth current terminals and the current source; and
a comparator having a first input, a second input and an output, in which the first input is coupled to the first current terminal, the second input is coupled to the fifth current terminal, and the output of the comparator coupled to the detector output.
2 . The apparatus of claim 1 , wherein the first filter has a first time constant, the second filter has a second time constant, and the envelope detector has a decay time based on the first and second time constants.
3 . The apparatus of claim 1 , wherein the first and second transistors are configured to, responsive to receiving a first voltage at the first control terminal and a second voltage at the second control terminal, store a third voltage in the first filter based on a peak value of the first and second voltages.
4 . The apparatus of claim 1 , wherein the third and fourth transistors are configured to, responsive to receiving a first voltage at the third control terminal and a second voltage at the fourth control terminal, store a third voltage in the second filter based on a peak value of the first and second voltages.
5 . An apparatus, comprising:
a first differential pair of transistors;
a second differential pair of transistors;
a first capacitor coupled between a power terminal and first current terminals of the first differential pair of transistors;
a second capacitor coupled between the power terminal and first current terminals of the second differential pair of transistors;
a current source coupled between second current terminals of the first and second differential pairs of transistors and a reference terminal, the current source configured to provide a bias current to the first and second differential pairs of transistors;
and
a comparator having a negative input and a positive input, in which the negative input is coupled to the first current terminals, and the positive input is coupled to the second current terminals.
6 . The apparatus of claim 5 , wherein the first differential pair of transistors are configured to receive a first voltage and a second voltage at their inputs and store a third voltage based on a peak value of the first and second voltages at the first capacitor, and the second differential pair of transistors are configured to receive a fourth voltage and a fifth voltage at their inputs and store a sixth voltage based on a peak value of the fourth and fifth voltages at the second capacitor.
7 . The apparatus of claim 6 , further comprising a first resistor coupled between the power terminal and the first current terminals of the first differential pair of transistors and a second resistor coupled between the power terminal and the first current terminals of the second differential pair of transistors.
8 . The apparatus of claim 7 , wherein the first capacitor and the first resistor form a first filter, and the second capacitor and the second resistor form a second filter.
9 . The apparatus of claim 5 , further comprising a resistor coupled between the second current terminals of one of the first or second differential pair of transistors and the current source.
10 . The apparatus of claim 8 , wherein the first filter has a first time constant, the second filter has a second time constant, the first and second differential pairs of transistors are part of an envelope detector, and a decay time of the envelope detector being configured based on the first and second time constants.
11 . The apparatus of claim 5 , wherein the apparatus is part of a demodulator comprising a preamplifier, the preamplifier having first differential outputs coupled to first differential inputs of the first differential pair of transistors and second differential outputs coupled to second differential inputs of the second differential pair of transistors.
12 . A circuit, comprising:
a first differential pair of transistors having a first terminal and a second terminal;
a first resistor capacitor (RC) network coupled between a power terminal and the first terminal;
a second differential pair of transistors having a third terminal and a fourth terminal;
a second RC network coupled between the power terminal and the third terminal;
a current source coupled between the second and fourth terminals and a reference terminal, the current source configured to provide a bias current to the first and second differential pairs of transistors;
a resistor coupled between one of the second or fourth terminals and the current source; and
a comparator having a negative input and a positive input, in which the negative input is coupled to the first terminal, and the positive input is coupled to the third terminal.
13 . The circuit of claim 12 , wherein:
the first differential pair comprises:
a first transistor having a first control terminal, a first current terminal and a second current terminal, in which the first current terminal is coupled to the first terminal, and the second current terminal is coupled to the second terminal; and
a second transistor having a second control terminal, a third current terminal and a fourth current terminal, in which the third current terminal is coupled to the first terminal, and the fourth current terminal is coupled to the second terminal; and
the second differential pair comprises:
a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, in which the fifth current terminal is coupled to the third terminal, and the sixth current terminal is coupled to the fourth terminal; and
a fourth transistor having a fourth control terminal, a seventh current terminal and an eighth current terminal, in which the seventh current terminal is coupled to the third terminal, and the eighth current terminal is coupled to the fourth terminal.
14 . The circuit of claim 12 , wherein the first differential pair of transistors are configured to receive a first voltage and a second voltage at their inputs and store a third voltage based on a peak value of the first and second voltages at the first RC network, and the second differential pair of transistors are configured to receive a fourth voltage and a fifth voltage at their inputs and store a sixth voltage based on a peak value of the fourth and fifth voltages at the second RC network.
15 . The circuit of claim 12 , wherein the first RC network has a first time constant, the second RC network has a second time constant, and the circuit has a decay time based on the first and second time constants.
16 . The circuit of claim 12 , further comprising a preamplifier coupled to first differential inputs of the first differential pair of transistors and second differential inputs of the second differential pair of transistors.