IP Library › Granted Patent US 12671412
Granted Patent B2
US 12671412 · App. 18/631,931 · Granted Jun 30, 2026

Double gate transistor device and method of operating

Inventors: Markus Bina (Kolbermoor, DE); Jens Barrenscheen (Munich, DE); Anton Mauder (Kolbermoor, DE)
Assignee: Infineon Technologies Austria AG
H03K17/567H03K17/687H10D12/481H10D30/475H10D30/477H10D30/611H10D30/668H10D48/362H10D62/165H10D64/117H10D64/256H10D64/513H03K2017/6878H10D62/343H10D62/8503
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Quick Facts
Patent No.
US 12671412
App. No.
18/631,931
Granted
Jun 30, 2026
Kind
B2
Abstract

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Claims (42)

1 . A transistor device comprising:

at least one transistor cell comprising:

a drift region, a body region, a source region and a drain region, wherein the body region is arranged between the source region and the drift region, and wherein the drift region is arranged between the body region and the drain region;

a first gate electrode dielectrically insulated from the body region by a first gate dielectric; and

a second gate electrode,

wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a first separation layer; and

a second separation layer located between the first gate electrode and the second gate electrode, wherein the second separation layer is oriented in a different direction than the first separation layer, and wherein the second separation layer is thicker than the first gate dielectric and the second gate dielectric.

2 . The transistor device of claim 1 , further comprising a plurality of transistor cells,

wherein each of the plurality of transistor cells has its respective source region connected to a source node common to the plurality of transistor cells,

wherein each of the plurality of transistor cells has its respective first gate electrode connected to a first gate node common to the plurality of transistor cells, and

wherein each of the plurality of transistor cells has its respective second gate electrode connected to a second gate node common to the plurality of transistor cells.

3 . The transistor device of claim 1 , wherein the first separation layer includes a dielectric layer.

4 . The transistor device of claim 1 , wherein the drain region has a doping concentration higher than a doping concentration of the drift region.

5 . The transistor device of claim 4 , wherein the doping concentration of the drain region is at least 1E3 times or 1E4 times the doping concentration of the drift region.

6 . The transistor device of claim 4 , wherein a doping type of the drain region equals a doping type of the drift region.

7 . The transistor device of claim 4 , wherein a doping type of the drain region is complementary to a doping type of the drift region.

8 . The transistor device of claim 1 , wherein the transistor device includes a current flow direction, and wherein the second gate electrode is adjacent the first gate electrode in the current flow direction.

9 . The transistor device of claim 1 , wherein the first gate dielectric, the second gate dielectric and the first separation layer comprise the same type of material.

10 . The transistor device of claim 1 , further comprising a channel region configured to provide a continuous conducting channel in the body region between the source region and the drift region.

11 . A transistor device comprising a plurality of transistor cells, each transitor cell comprising:

a drift region, a body region, a source region and a drain region, wherein the body region is arranged between the source region and the drift region, and wherein the drift region is arranged between the body region and the drain region;

a first gate electrode dielectrically insulated from the body region by a first gate dielectric; and

a second gate electrode,

wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a first separation layer; and

a second separation layer located between the first gate electrode and the second gate electrode, wherein the second separation layer is oriented in a different direction than the first separation layer, wherein the second separation layer is thicker than the first gate dielectric and the second gate dielectric,

wherein each of the plurality of transistor cells has its respective source region connected to a source node common to the plurality of transistor cells,

wherein each of the plurality of transistor cells has its respective first gate electrode connected to a first gate node common to the plurality of transistor cells, and

wherein each of the plurality of transistor cells has its respective second gate electrode connected to a second gate node common to the plurality of transistor cells.

12 . The transistor device of claim 11 , wherein each transistor cell includes a current flow direction, and wherein the second gate electrode of each particular transistor cell is adjacent the first gate electrode of the particular transistor cell in the current flow direction.

13 . The transistor device of claim 11 , wherein the first gate dielectric, the second gate dielectric and the first separation layer comprise the same type of material.

14 . The transistor device of claim 11 , further comprising a channel region configured to provide a continuous conducting channel in the body region between the source region and the drift region.

15 . A transistor device comprising:

at least one transistor cell comprising:

a drift region, a body region, a source region and a drain region, wherein the body region is arranged between the source region and the drift region, and wherein the drift region is arranged between the body region and the drain region;

a first gate electrode dielectrically insulated from the body region by a first gate dielectric; and

a second gate electrode,

wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a first separation layer;

a channel region; and

a second separation layer located between the first gate electrode and the second gate electrode, wherein the second separation layer is oriented in a different direction than the first separation layer, and wherein the second separation layer is thicker than the first gate dielectric and the second gate dielectric.

16 . The transistor device of claim 15 , wherein the first gate dielectric, the second gate dielectric and the first separation layer comprise the same type of material.

17 . The transistor device of claim 15 , wherein the transistor device is configured to control switching of loads.

18 . The transistor device of claim 15 , wherein the first gate electrode and the second gate electrode are configured to control different portions of the same channel region between the source region and the drift region.