Gate driver circuit and operating method thereof
A gate driver circuit and an operating method thereof are provided. The gate driver circuit includes a charge sharing circuit including a first resistor, a second resistor, a first capacitor, a second capacitor, a first switching transistor, and a second switching transistor. A first terminal of the first resistor is coupled to a first working voltage. A first terminal of the first capacitor is coupled to a second terminal of the first resistor, and a second terminal is coupled to a second working voltage. A first terminal of the first switching transistor is coupled to the second terminal of the first resistor and the first terminal of the first capacitor, and a second terminal is coupled to a circuit node. A first terminal of the second switching transistor is coupled to the circuit node.
1 . A gate driver circuit, comprising:
a charge sharing circuit, comprising:
a first resistor, wherein a first terminal of the first resistor is coupled to a first working voltage;
a first capacitor, wherein a first terminal of the first capacitor is coupled to a second terminal of the first resistor, and a second terminal of the first capacitor is coupled to a second working voltage;
a first switching transistor, wherein a first terminal of the first switching transistor is coupled to the second terminal of the first resistor and the first terminal of the first capacitor, a control terminal of the first switching transistor receives a first switching signal, and a second terminal of the first switching transistor is coupled to a circuit node;
a second switching transistor, wherein a first terminal of the second switching transistor is coupled to the circuit node, and a control terminal of the second switching transistor receives a second switching signal;
a second capacitor, wherein a first terminal of the second capacitor is coupled to a second terminal of the second switching transistor, and a second terminal of the second capacitor is coupled to the second working voltage; and
a second resistor, wherein a first terminal of the second resistor is coupled to the second terminal of the second switching transistor, and a second terminal of the second resistor is coupled to the second working voltage.
2 . The gate driver circuit according to claim 1 , wherein a conduction period of the first switching transistor and a conduction period of the second switching transistor are non-overlapping and have a time interval.
3 . The gate driver circuit according to claim 1 , wherein the first switching transistor is a P-type transistor, and the second switching transistor is an N-type transistor.
4 . The gate driver circuit according to claim 1 , further comprising:
a potential transducer, coupled to the charge sharing circuit and used to receive a first input signal and a second input signal, and convert potentials of the first input signal and the second input signal to generate the first switching signal and the second switching signal.
5 . The gate driver circuit according to claim 4 , wherein the potential transducer comprises:
a first operational amplifier, wherein a first input terminal of the first operational amplifier receives the first input signal, and an output terminal of the first operational amplifier is coupled to the control terminal of the first switching transistor; and
a second operational amplifier, wherein a first input terminal of the second operational amplifier receives the second input signal, and an output terminal of the second operational amplifier is coupled to the control terminal of the second switching transistor.
6 . The gate driver circuit according to claim 5 , wherein the potential transducer further comprises:
a first voltage dividing resistor, coupled between a second input terminal of the first operational amplifier and a reference voltage;
a second voltage dividing resistor, coupled between the output terminal of the first operational amplifier and the second input terminal of the first operational amplifier;
a third voltage dividing resistor, coupled between a second input terminal of the second operational amplifier and the reference voltage; and
a fourth voltage dividing resistor, coupled between the output terminal of the second operational amplifier and the second input terminal of the second operational amplifier.
7 . The gate driver circuit according to claim 4 , further comprising:
a non-overlapping double pulse generator, coupled to the potential transducer, receiving a control signal, and generating the first input signal and the second input signal according to the control signal,
wherein a rising edge and a falling edge of each pulse wave of the first input signal and a rising edge and a falling edge of each pulse wave of the second input signal are non-overlapping.
8 . The gate driver circuit according to claim 7 , wherein the control signal is a pulse width modulation signal.
9 . The gate driver circuit according to claim 7 , wherein the non-overlapping double pulse generator comprises:
a first buffer, wherein an input terminal of the first buffer receives the control signal;
a first inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the first buffer;
a first AND gate, wherein a first input terminal of the first AND gate is coupled to an output terminal of the first inverter;
a second buffer, wherein an input terminal of the second buffer is coupled to an output terminal of the first AND gate, and an output terminal of the second buffer is coupled to the non-overlapping double pulse generator to output the first input signal;
a second inverter, wherein an input terminal of the second inverter is coupled to the output terminal of the first buffer;
a resistor, wherein a first terminal of the resistor is coupled to an output terminal of the second inverter;
a capacitor, wherein a first terminal of the capacitor is coupled to a second terminal of the resistor, and a second terminal of the capacitor is coupled to a ground voltage;
a third inverter, wherein an input terminal of the third inverter is coupled to the second terminal of the resistor;
a fourth inverter, wherein an input terminal of the fourth inverter is coupled to an output terminal of the third inverter, and an output terminal of the fourth inverter is coupled to a second input terminal of the first inverter;
a second AND gate, wherein a first input terminal of the second AND gate is coupled to the output terminal of the third inverter, and a second input terminal of the second AND gate is coupled to the output terminal of the first buffer; and
a fifth inverter, wherein an input terminal of the fifth inverter is coupled to an output terminal of the second AND gate, and an output terminal of the fifth inverter is coupled to the non-overlapping double pulse generator to output the second input signal.
10 . The gate driver circuit according to claim 1 , wherein the charge sharing circuit further comprises:
an output resistor, wherein a first terminal of the output resistor is coupled to the circuit node, and a second terminal of the output resistor is coupled to a gate of a power transistor.
11 . An operating method, adapted to a gate driver, wherein the gate driver comprises a charge sharing circuit, wherein the charge sharing circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a first switching transistor, and a second switching transistor,
wherein a first terminal of the first resistor is coupled to a first working voltage,
wherein a first terminal of the first capacitor is coupled to a second terminal of the first resistor, and a second terminal of the first capacitor is coupled to a second working voltage,
wherein a first terminal of the first switching transistor is coupled to the second terminal of the first resistor and the first terminal of the first capacitor, and a second terminal of the first switching transistor is coupled to a circuit node,
wherein a first terminal of the second switching transistor is coupled to the circuit node,
wherein a first terminal of the second capacitor is coupled to a second terminal of the second switching transistor, and a second terminal of the second capacitor is coupled to the second working voltage,
wherein a first terminal of the second resistor is coupled to the second terminal of the second switching transistor, and a second terminal of the second resistor is coupled to the second working voltage,
the operating method comprising:
receiving a first switching signal through a control terminal of the first switching transistor; and
receiving a second switching signal through a control terminal of the second switching transistor,
wherein a conduction period of the first switching transistor and a conduction period of the second switching transistor are non-overlapping and have a time interval.
12 . The operating method according to claim 11 , further comprising:
receiving a first input signal and a second input signal through a potential transducer; and
converting potentials of the first input signal and the second input signal through the potential transducer to generate the first switching signal and the second switching signal.
13 . The operating method according to claim 12 , further comprising:
receiving a control signal through a non-overlapping double pulse generator; and
generating the first input signal and the second input signal according to the control signal through the non-overlapping double pulse generator,
wherein a rising edge and a falling edge of each pulse wave of the first input signal and a rising edge and a falling edge of each pulse wave of the second input signal are non-overlapping.
14 . The operating method according to claim 13 , wherein the control signal is a pulse width modulation signal.