Processing method, asynchronous circuit, and logic circuit

1 . A processing method comprising:

causing a computer to perform first processing for identifying one or a plurality of flip-flop circuits each forming a self-feedback loop from among a plurality of flip-flop circuits in a synchronous circuit, deleting a feedback path in the self-feedback loop, identifying two or more flip-flop circuits forming strongly coupled components from among the one or plurality of flip-flop circuits, and replacing the two or more flip-flop circuits forming the strongly coupled components with one dummy flip-flop circuit; and

causing the computer to perform second processing for alternately performing processing for searching for one or more flip-flop circuits coupled to input side of one or more flip-flop circuits out of the plurality of flip-flop circuits including the dummy flip-flop circuit through a combinational circuit, and processing for searching for one or more flip-flop circuits coupled to output side of the searched one or more flip-flop circuits through the combinational circuit a plurality of times to thereby identify first one or more flip-flop circuits coupled to input side of the combinational circuit and second one or more flip-flop circuits coupled to output side of the combinational circuit.

2 . The processing method according to claim 1 , wherein

the second processing includes

causing the computer to perform third processing for sequentially selecting one of the plurality of flip-flop circuits including the dummy flip-flop circuit,

causing the computer to perform fourth processing for identifying, as a first set, one or a plurality of flip-flop circuits coupled to first side that is one of input side and output side of the flip-flop circuit selected by the third processing through a combinational circuit, and identifying, as a second set, one or a plurality of flip-flop circuits coupled to second side that is the other of the input side and the output side of each of the one or plurality of flip-flop circuits included in the first set through the combinational circuit,

causing the computer to repeatedly perform fifth processing once or a plurality of times, the fifth processing being for identifying, as a first set different from the latest first set, one or a plurality of flip-flop circuits coupled to the first side of each of the one or plurality of flip-flop circuits included in the latest second set through the combinational circuit, and identifying, as a second set different from the latest second set, one or a plurality of flip-flop circuits coupled to the second side of each of the one or plurality of flip-flop circuits included in the latest first set through the combinational circuit, and

causing the computer to perform sixth processing for confirming whether or not a determination condition that latest two of the first sets are equal to each other and latest two of the second sets are equal to each other is satisfied every time the fifth processing is performed, and specifying the first one or more flip-flop circuits and the second one or more flip-flop circuits on a basis of the latest two of the first sets and the latest two of the second sets in a case where the determination condition is satisfied.

3 . The processing method according to claim 1 , further comprising causing the computer to perform seventh processing in a case where the second one or more flip-flop circuits specified by the second processing form the self-feedback loop, the seventh processing being for converting each of the second one or more flip-flop circuits into four stages of latch circuits, converting the combinational circuit into four combinational circuits by logically dividing the combinational circuit into four in a logical stage number direction, and alternately disposing one of the four combinational circuits and one of the four stages of latch circuits.

4 . The processing method according to claim 3 , further comprising causing the computer to perform eighth processing for preparing a handshake circuit that performs handshake processing with one or both of a preceding-stage circuit and a subsequent-stage circuit, and supplies four control signals to the respective four stages of latch circuits.

5 . The processing method according to claim 3 , further comprising causing the computer to perform ninth processing for converting a first circuit into a second circuit, the first circuit in which one of the four combinational circuits obtained by the seventh processing and one of the four stages of latch circuits are alternately disposed, and the second circuit including the four combinational circuits and two stages of latch circuits, wherein

in the second circuit,

one of a piece of output data of a first stage of combinational circuit of the four stages of combinational circuits and a piece of output data of a third stage of combinational circuit is selectively supplied to a first stage of latch circuit out of the two stages of latch circuits,

a piece of output data of the first stage of latch circuit is selectively supplied to one of a second combinational circuit and a fourth combinational circuit out of the four combinational circuits,

one of a piece of output data of the second combinational circuit and a piece of output data of the fourth combinational circuit is selectively supplied to a second stage of latch circuit out of the two stages of latch circuits, and

a piece of output data of the second stage of latch circuit is selectively supplied to one of the first combinational circuit and the third combinational circuit.

6 . The processing method according to claim 5 , further comprising causing the computer to perform tenth processing for preparing a handshake circuit that performs handshake processing with one or both of a preceding-stage circuit and a subsequent-stage circuit, and supplies two control signals to the respective two stages of latch circuits.

7 . The processing method according to claim 1 , further comprising causing the computer to perform eleventh processing in a case where the second one or more flip-flop circuits specified by the second processing do not form the self-feedback loop, the eleventh processing being for converting each of the second one or more flip-flop circuits into two stages of latch circuits, converting the combinational circuit into two combinational circuits by logically dividing the combinational circuit into two in a logical stage number direction, and alternately disposing one of the two combinational circuits and one of the two stages of latch circuits.