Systems, methods, and apparatus to support multiple synchronous clocks with a single clock mesh
A single clock mesh is configured to provide a first clock signal at a first frequency. A number of divided clock signals are generated, each divided clock signal being at a frequency that is a respective integer division of the first frequency. The divided clock signals are received from a divider and output by a clock controller along with corresponding enable signals. For each divided clock, a shaped clock signal is generated. The shaped clock signal has rising edges and falling edges that algin with rising edges and falling edges of the first clock signal provided by the single clock mesh.
1 . An electronic device for supporting multiple synchronous clocks with a single clock mesh, the electronic device comprising:
a single clock mesh configured to provide a first clock signal at a first frequency;
divider circuitry configured to generate a plurality of divided clock signals, each divided clock signal being at a frequency that is a respective integer division of the first frequency;
an on-chip clock controller configured to receive the divided clock signals, and output the divided clock signals and corresponding enable signals for each divided clock signal; and
clock shaper circuitry configured to generate, for each divided clock signal, a shaped clock signal having rising edges and falling edges aligned with rising edges and falling edges of the first clock signal provided by the single clock mesh.
2 . The electronic device of claim 1 , further comprising:
a multiplexer configured to receive the divided clock signals and corresponding enable signals from the on-chip clock controller and transmit, for each respective divided clock signal, one of the respective divided clock signal or its corresponding enable signal.
3 . The electronic device of claim 1 , further comprising:
a plurality of flip flops arranged in a sequence of flip flops such that an output of any first flip flop of the plurality of flip flops, other than a last flip flop, is input into a next flip flop in the sequence, wherein a divided clock signal from the on-chip clock controller is input into the sequence of flip flops and output, from the last flip flop of the sequence of flip flops, to the clock shaper circuitry.
4 . The electronic device of claim 3 , wherein the plurality of flip flops comprises a tree of flip flops allowing the signal to be duplicated and sent along parallel paths to different receiving components.
5 . The electronic device of claim 3 , wherein the plurality of flip flops is configured to ensure that each divided clock signal arrives at the clock shaper circuitry during a first clock cycle.
6 . The electronic device of claim 1 , further comprising control circuitry configured to:
select one or more of the plurality of divided clock signals; and
gate the selected one or more divided clock signals.
7 . The electronic device of claim 6 , further comprising:
a respective plurality of flip flops coupled to the output of the clock shaper circuitry for each divided clock signal; wherein:
the control circuitry is further configured to, while gating at least one of the plurality of divided clock signals, scan the respective plurality of flip flops associated with the at least one of the plurality of divided clock signals.
8 . A method for supporting multiple synchronous clocks with a single clock mesh, the method comprising:
providing a first clock signal at a first frequency using a single clock mesh;
generating a plurality of divided clock signals, each divided clock signal being at a frequency that is a respective integer division of the first frequency;
receiving the divided clock signals and outputting the divided clock signals and corresponding enable signals for each divided clock signal; and
generating, for each divided clock signal, a shaped clock signal having rising edges and falling edges aligned with rising edges and falling edges of the first clock signal provided by the single clock mesh.
9 . The method of claim 8 , further comprising:
receiving the divided clock signals and corresponding enable signals and transmitting, for each respective divided clock signal, one of the respective divided clock signal or its corresponding enable signal.
10 . The method of claim 8 , further comprising:
delaying transmission of a divided clock signal to ensure transmission of the divided clock signal after a specific number of clock cycles.
11 . The method of claim 10 , further comprising delaying transmission of a second divided clock signal to ensure that the divided clock signal and the second divided clock signal are transmitted during the same clock cycle.
12 . The method of claim 8 , further comprising:
selecting one or more of the plurality of divided clock signals; and
gating the selected one or more divided clock signals.
13 . The method of claim 12 , further comprising, while gating at least one of the plurality of divided clock signals, scanning a plurality of flip flops associated with the at least one of the plurality of divided clock signals.
14 . The method of claim 13 , further comprising generating a scan clock signal at a frequency that is below a frequency of the respective divided clock signal associated with the plurality of flip flops.
15 . A system for supporting multiple synchronous clocks with a single clock mesh, comprising:
a clock mesh configured to provide a first clock signal at a first frequency;
one or more electronic components, each of which is configured to operate using a respective clock signal at a respective different frequency lower than the first frequency, the respective different frequency being an integer division of the first frequency, a plurality of different frequencies being used among the one or more electronic components; and
clock circuitry configured to:
generate, from the first clock signal, one or more divided clock signals, wherein each divided clock signal has a frequency that is an integer division of the first frequency, and wherein each respective divided clock signal corresponds to a respective frequency among the plurality of different frequencies, and
shape each of the one or more divided clock signals such that each divided clock signal has a rising edge that aligns with a rising edge of the first clock signal and a falling edge that aligns with a falling edge of the first clock signal.
16 . The apparatus of claim 15 , further comprising:
a multiplexer configured to receive the divided clock signals and corresponding enable signals and transmit, for each respective divided clock signal, one of the respective divided clock signal or its corresponding enable signal.
17 . The system of claim 15 , further comprising:
a plurality of flip flops, the plurality of flip flops being arranged in a sequence of flip flops such than an output of a first flip flop of the plurality of flip flops is input into a next flip flop in the sequence, wherein a divided clock signal is input into the sequence of flip flops and output, from a last flip flop of the sequence of flip flops, to the clock circuitry configured to shape each divided clock signal.
18 . The system of claim 17 , wherein the plurality of flip flops is configured to ensure that each divided clock signal arrives at the control circuitry configured to shape each divided clock signal during the same clock cycle.
19 . The system of claim 15 , further comprising control circuitry configured to:
select one or more of the plurality of divided clock signals; and
gate the selected one or more divided clock signals.
20 . The system of claim 19 , further comprising:
a respective plurality of flip flops coupled to an output of the clock shaper circuitry for each divided clock signal; wherein:
the control circuitry is further configured to, while gating at least one of the plurality of divided clock signals, scan the respective plurality of flip flops associated with the at least one of the plurality of divided clock signals.