Clock and data recovery circuit suitable for high-speed SerDes and recovery method

1 . A clock and data recovery circuit suitable for high-speed SerDes, comprising:

an analog front end, which inputs a receiving signal and outputs a result of a phase detector;

a phase discrimination accumulator, which is used for accumulating the result of the phase detector;

a gain control unit, which is used for adjusting a gain of a trunk signal;

a first branch, which comprises a proportion voter and a phase gain unit;

a second branch, which comprises a weight voter and a frequency integration unit;

an adder, which is used for adding output results of the phase gain unit and the frequency integration unit, wherein an output of the adder sequentially passes through a phase accumulator and a phase interpolator; and

the phase interpolator, which is used for outputting a sampling clock for the analog front end to use;

wherein, the weight voter is used for linear amplification when an absolute value of an accumulative value of phase discrimination exceeds a weight limit value, no adjustment is made when the absolute value of the accumulative value of phase discrimination does not exceed the weight limit value, and the weight voter is expressed as follows:

Kv

⁢

2

=

{

0

,

❘

"\[LeftBracketingBar]"

pd

❘

"\[RightBracketingBar]"

<

α

γ

,

❘

"\[LeftBracketingBar]"

pd

❘

"\[RightBracketingBar]"

≥

α

(

1

)

wherein, γ is a gain coefficient of the weight voter, α is the set weight limit value, pd is the accumulative value of phase discrimination, and Kv2 is an output of the weight voter; and

the proportion voter is used for linear amplification under any accumulative value of phase discrimination, and the proportion voter is expressed as follows:

Kv

⁢

1

=

β

(

2

)

wherein, β is a gain coefficient of the proportion voter, and Kv1 is an output of the proportion voter.

2 . The clock and data recovery circuit suitable for high-speed SerDes according to claim 1 , wherein the frequency integration unit is further provided with a frequency offset limiter, and a maximum value of an allowable frequency offset is set for the frequency offset limiter.

3 . The clock and data recovery circuit suitable for high-speed SerDes according to claim 1 , wherein the phase interpolator is further provided with a jump step size limiter, and a maximum value of an allowable phase jump is set for the jump step size limiter.

4 . A clock and data recovery method suitable for high-speed SerDes adopting the clock and data recovery circuit suitable for high-speed SerDes according to claim 1 , comprising the following steps of:

receiving a signal by the analog front end, then subjecting the received signal to front-end processing under an action of the sampling clock, outputting results of multiple phase detectors, and accumulating the results of the multiple phase detectors to obtain the accumulative value of phase discrimination;

when the accumulative value of phase discrimination is less than the preset weight limit value, adjusting the phase gain unit only, and when the accumulative value of phase discrimination is greater than the preset weight limit value, synchronously adjusting the phase gain unit and the frequency integration unit;

adding the results of the phase gain unit and the frequency integration unit by the adder, and then allowing the output of the adder to sequentially pass through the phase accumulator and the phase interpolator, so as to output the adjusted sampling clock, wherein the sampling clock is provided for the analog front end to use; and

under constant adjustment of the sampling clock until CDR locking, recovering the sampling clock, and recovering data by the analog front end.

5 . The clock and data recovery method suitable for high-speed SerDes according to claim 4 , wherein a specific adjustment method comprises: inputting the accumulative value of phase discrimination into the first branch and the second branch at the same time, wherein, in the first branch, under an action of the proportion voter, when the accumulative value of phase discrimination is positive, the phase gain unit is adjusted positively, when the accumulative value of phase discrimination is negative, the phase gain unit is adjusted negatively, and when the accumulative value of phase discrimination is zero, a current sampling clock phase is appropriate, and the phase gain unit is not adjusted; and

in the second branch, under an action of the weight voter, in a case that the absolute value of the accumulative value of phase discrimination is greater than the preset weight limit value, when the accumulative value of phase discrimination is positive, the frequency integration unit is adjusted positively, and when the accumulative value of phase discrimination is negative, the frequency integration unit is adjusted negatively, and in a case that the absolute value of the accumulative value of phase discrimination is not greater than the preset weight limit value, the frequency integration unit is not adjusted.

6 . The clock and data recovery method suitable for high-speed SerDes according to claim 4 , wherein a specific adjustment method comprises: in an adjustment process of the frequency integration unit, limiting a maximum value of a frequency offset, and making a frequency offset step size fall within a maximum value range.

7 . The clock and data recovery method suitable for high-speed SerDes according to claim 4 , wherein a specific adjustment method comprises: in a phase interpolation process, limiting a maximum value of a jump step size of the phase interpolator, and making the phase jump step size fall within a maximum value range.