High speed precision frontend

1 . A circuit comprising:

an input amplifier arranged to receive an input signal, the input amplifier introducing into the input signal an error voltage;

a feed-forward signal path being arranged such that it conveys an error signal representative of the error voltage; and

error cancellation circuitry arranged to operate on the input signal and the error signal to cancel the error voltage from the input signal; and

an impedance network coupled to an input and an output of the input amplifier where an output of the impedance network forms part of the feed-forward signal path, the impedance network comprising at least one potential divider.

2 . The circuit of claim 1 , wherein the input amplifier is arranged to receive an input signal to be digitized, and wherein the error cancellation is arranged such that the digitized input signal has the error voltage cancelled therefrom.

3 . The circuit of claim 1 , wherein the feed-forward signal path comprises at least one feed-forward active component.

4 . The circuit of claim 3 , wherein the at least one feed-forward active component is an amplifier.

5 . The circuit of claim 1 , wherein the input amplifier is further arranged such that the input signal including the error voltage is fed to a main analog-to-digital converter (ADC) for digitization.

6 . The circuit of claim 1 , wherein the feed-forward signal path comprises a feed-forward ADC channel.

7 . The circuit of claim 6 , wherein the error cancellation circuitry operates on the input signal that includes the error voltage on a main ADC channel and an error signal on a feed-forward ADC channel and further arranged to separately digitize:

(i) the input signal via a main ADC; and

(ii) the error signal via a feed-forward ADC; and

combines a digital representation of the error signal from the feed-forward ADC with a digital representation of the input signal from the main ADC, for use in cancelling the error voltage contained therein.

8 . The circuit of claim 1 , wherein a multiplier is positioned in the feed-forward signal path, the multiplier being arranged to scale and/or invert the signal from an ADC, prior to being applied to the error cancellation circuitry; and/or

a multiplier is positioned on the output of the main ADC the multiplier being arranged to scale and/or invert the output from the main ADC, prior to being applied to the error cancellation circuitry.

9 . The circuit of claim 1 , wherein the error cancellation circuitry operates on the input signal on a main ADC channel and an error signal on a feed-forward ADC channel, the main ADC channel and the feed-forward ADC channel being channels of a two channel main ADC, the two channel main ADC digitizes a combined input signal and error signal to produce a single digitized output such that the digitized output has the error voltage cancelled therefrom.

10 . The circuit of claim 9 , wherein the two channel main ADC comprises a first channel and a second channel, the first channel comprising: a first switch and a first capacitor in series, the second channel comprising: a second switch and a second capacitor in series, wherein the first switch of the first channel of the two channel main ADC is used to sample and hold the input signal including the error voltage on the first capacitor, the second switch is used to sample and hold the error signal on the second capacitor.

11 . The circuit of claim 10 , wherein the first channel and second channel of the two channel main ADC are arranged such that when the input signal including the error Ve is acquired on the first capacitor and the error signal is acquired on the second capacitor the two channel main ADC digitizes the combined input signal and the error signal to produce the digitized output; and

wherein the capacitance of the first capacitor in the first channel and the capacitance of the second capacitor in the second channel are scaled to cancel the error voltage in the two channel main ADC.

12 . The circuit of claim 1 , wherein the feed-forward signal path further comprises a third capacitor, the third capacitor being arranged to sample the error signal prior to gain in the feed-forward signal path.

13 . The circuit of claim 1 , wherein the drive circuit is arranged such that a bandwidth of the drive circuit first sampling the input signal including the error Ve and a bandwidth of the drive circuit first sampling the error signal are substantially matched and the first sampling of the input signal including the error Ve and the first sampling of the error signal occur at substantially the same time.

14 . The circuit of claim 1 , wherein the error cancellation circuitry comprises a first resistor in an input signal path and a second resistor in an error signal path, the first resistor and the second resistor both being connected to an output node and being arranged such that the error voltage is cancelled from the input signal by the overall ratio of the network resistances at the output node.

15 . The circuit of claim 1 , wherein the at least one potential divider comprises a first potential divider connected between the output of the input amplifier and an input node and having an output connected to the input of the input amplifier, and a second potential divider connected between the output of the input amplifier and the input node and having an output connected to an input of the feed-forward signal path.

16 . A circuit for a two channel analog-to-digital converter (ADC), the circuit comprising:

an input amplifier arranged to receive an input signal to be digitized by a main ADC channel, the input amplifier introducing into the input signal an error voltage, the input signal including the error voltage being input into the main ADC channel;

a feed-forward signal path comprising a feed-forward analog-to-digital converter (ADC) channel that receives an error signal representative of the error voltage;

error cancellation circuitry arranged to operate on the signals on the main ADC channel and the feed-forward ADC channel, the main ADC channel and the feed-forward ADC channel being channels of a two channel ADC, the ADC digitizes the combined input signal and the error signal to produce a digitized output such that the digitized output has the error voltage cancelled therefrom; and

an impedance network coupled to an input and an output of the input amplifier where an output of the impedance network forms part of the feed-forward signal path, the impedance network comprising at least one potential divider.

17 . The circuit of claim 16 , the two channel ADC channel comprising: a first switch and a first capacitor arranged in series, the feed-forward ADC channel comprising: a second capacitor arranged in series, wherein the first switch of the first channel of the two channel ADC is used to sample and hold the input signal on the first capacitor, the error signal is sampled and held on the second capacitor.

18 . The circuit of claim 17 , the drive circuit being arranged such that the error signal is acquired on the feed-forward ADC channel during a second time period; and

such that the two channel ADC digitizes the combined input signal including the error voltage and the error signal to produce a digitized output during a third time period, wherein the third time period occurs after the second time period and the second time period occurs after the first time period.

19 . The circuit of claim 16 , wherein the at least one potential divider comprises a first potential divider connected between the output of the input amplifier and an input node and having an output connected to the input of the input amplifier, and a second potential divider connected between the output of the input amplifier and the input node and having an output connected to an input of the feed-forward signal path.

20 . A circuit for a main analog-to-digital converter (ADC), the circuit comprising:

an input amplifier arranged to receive an input signal to be digitized by a main ADC channel, the input amplifier introducing into the input signal an error voltage, the input signal including the error voltage being input into the main ADC channel for digitization;

a feed-forward signal path comprising a feed-forward analog-to-digital converter (ADC) channel that receives an error signal representative of the error voltage for digitization;

error cancellation circuitry arranged to operate on the signals on the main ADC channel and the feed-forward ADC channel, and further arranged to separately digitize:

(i) the input signal via a main ADC; and

(ii) the error signal via a feed-forward ADC; and

combine a digital representation of the error signal with a digital representation of the input signal to cancel the error Voltage contained therein; and

an impedance network coupled to an input and an output of the input amplifier where an output of the impedance network forms part of the feed-forward signal path, the impedance network comprising at least one potential divider.

21 . The circuit of claim 20 , wherein the drive circuit is arranged such that the input signal is acquired by the main ADC and the error signal is acquired on a capacitor arranged in the feed-forward signal path during a first time period; and wherein during a second time period, the error signal is acquired by the feed-forward ADC, wherein the second time period occurs after the first sample time period.

22 . The circuit of claim 20 , wherein the at least one potential divider comprises a first potential divider connected between the output of the input amplifier and an input node and having an output connected to the input of the input amplifier, and a second potential divider connected between the output of the input amplifier and the input node and having an output connected to an input of the feed-forward signal path.