Analog-to-digital conversion circuit
An analog-to-digital conversion circuit includes: a variable gain amplifier; a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal. The decimation filter includes: a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and a first digital filter that receives the second digital signal as an input, and outputs the first digital signal.
1 . An analog-to-digital conversion circuit comprising:
a variable gain amplifier;
a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and
a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal, wherein
the decimation filter includes:
a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and
a first digital filter that receives the second digital signal as an input, and outputs the first digital signal,
the analog-to-digital conversion circuit further comprises a gain controller that changes the amplification factor based on a value of the first digital signal, and
the gain controller changes the amplification factor as follows: (i) when an absolute value obtained by multiplying the value of the first digital signal by the amplification factor is greater than a first reference level, the amplification factor is halved; and (ii) when the absolute value is less than a second reference level that is less than half the first reference level, the amplification factor is doubled.
2 . The analog-to-digital conversion circuit according to claim 1 , wherein
the amplification factor is a power of two, and
the weight change unit includes:
a two's complement conversion circuit that converts the PDM signal into a third digital signal in two's complement notation which is weighted by a same weight as the PDM signal; and
a shift circuit that, when the amplification factor is two to a power of n where n is an integer of zero or more, performs an arithmetic shift of n bits on the third digital signal to output the second digital signal.
3 . The analog-to-digital conversion circuit according to claim 2 , wherein
the arithmetic shift of n bits is an arithmetic right shift of n bits.
4 . The analog-to-digital conversion circuit according to claim 1 , wherein
the decimation filter outputs the first digital signal in a first period, and
the gain controller changes the amplification factor in the first period.
5 . The analog-to-digital conversion circuit according to claim 1 , wherein
the delta-sigma modulator temporarily holds a value of the PDM signal in synchronization with a timing of the gain controller switching the amplification factor.
6 . An analog-to-digital conversion circuit comprising:
a variable gain amplifier;
a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and
a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal, wherein
the decimation filter includes:
a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and
a first digital filter that receives the second digital signal as an input, and outputs the first digital signal,
the first digital filter includes:
a second digital filter that receives the second digital signal as an input, and outputs a fourth digital signal having a total number of bits less than a total number of bits of the first digital signal; and
a third digital filter that receives the fourth digital signal as an input, and outputs the first digital signal,
the analog-to-digital conversion circuit further comprises a gain controller that changes the amplification factor based on a value of the fourth digital signal, and
the gain controller changes the amplification factor as follows: (i) when an absolute value obtained by multiplying the value of the first digital signal by the amplification factor is greater than a first reference level, the amplification factor is halved; and (ii) when the absolute value is less than a second reference level that is less than half the first reference level, the amplification factor is doubled.
7 . The analog-to-digital conversion circuit according to claim 6 , wherein
the delta-sigma modulator temporarily holds a value of the PDM signal in synchronization with a timing of the gain controller switching the amplification factor.
8 . The analog-to-digital conversion circuit according to claim 6 , wherein
the amplification factor is a power of two, and
the weight change unit includes:
a two's complement conversion circuit that converts the PDM signal into a third digital signal in two's complement notation which is weighted by a same weight as the PDM signal; and
a shift circuit that, when the amplification factor is two to a power of n where n is an integer of zero or more, performs an arithmetic shift of n bits on the third digital signal to output the second digital signal.
9 . The analog-to-digital conversion circuit according to claim 8 , wherein
the arithmetic shift of n bits is an arithmetic right shift of n bits.