Error correction

1 . A method, comprising:

partitioning a plurality of bits of a memory transfer block (MTB) into a plurality of pairs of bits;

generating symbols based on the partitioned pairs of bits and corresponding to each of the pair of bits;

communicating the plurality of pairs of bits of the MTB from a linked (LK) die to an interface (IF) die via a plurality of linked die input/output (LDIO) lines, wherein two pairs of bits of the plurality of pairs of bits are distributed to each LDIO line of the plurality of LDIO lines;

mapping the plurality of pairs of bits to pins of a data bus coupled to the IF die, wherein both of the two pairs of bits for each of the plurality of LDIO lines are mapped to the same pin of the data bus; and

responsive to detecting a failure on the data bus corresponding to one of the plurality of LDIO lines, performing a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the two pairs of bits mapped to the failed LDIO line, wherein each symbol corresponding to the plurality of pairs of bits is a respective symbol for the BCH error correction.

2 . The method of claim 1 , wherein the plurality of bits are communicated from the LK die, through the IF die, to the data bus absent storage of the plurality of bits in the IF die.

3 . The method of claim 1 , wherein partitioning the plurality of bits of the MTB comprises partitioning the plurality of bits evenly amongst the plurality of LDIO lines.

4 . The method of claim 1 , wherein partitioning the plurality of bits of the MTB comprises partitioning 144 bits of the MTB into 36 subsets of bits,

wherein each respective subset of bits comprises 2 of the plurality of pairs of bits of the MTB.

5 . The method of claim 1 , wherein communicating the plurality of pairs of bits of the MTB comprises communicating 2 of the plurality of pairs of bits of the MTB at a time via a respective LDIO line of the plurality.

6 . The method of claim 1 , wherein performing the BCH error correction comprises executing a quaternary BCH error correction code (ECC) on the pairs of bits mapped to the failed LDIO line.

7 . An apparatus, comprising:

a first linked (LK) die;

a first interface (IF) die coupled to the first LK die by a first plurality of LK die input/output (LDIO) lines;

control circuitry coupled to the first IF die and configured to direct:

association of a first plurality of subsets of bits of a memory transfer block (MTB) to respective ones of the first plurality of LDIO lines;

communication of the first plurality of subsets of bits from the first LK die to the first IF die via the first plurality of LDIO lines; and

responsive to an error in communication of the first plurality of subsets of bits, performance of a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the first plurality of subsets of bits;

a second LK die; and

a second IF die coupled to the second LK die by a second plurality of LDIO lines, wherein the control circuitry is coupled to the second IF die and is further configured to direct:

association of a second plurality of subsets of bits of the MTB to respective ones of the second plurality of LDIO lines;

communication of the second plurality of subsets of bits from the second LK die to the second IF die via the second plurality of LDIO lines; and

responsive to an error in communication of the second plurality of subsets of bits, performance of the BCH error correction on the second plurality of subsets of bits.

8 . The apparatus of claim 7 , wherein the control circuitry, the first IF die, the first LK die, the second IF die, and the second LK die are components of a Compute Express Link (CXL) compliant memory system.

9 . The apparatus of claim 7 , further comprising a first bus coupled to the first IF die and a second bus coupled to the second IF die, the first bus and the second bus comprising:

a plurality of pins dedicated to communication of data bits from the first IF die and the first LK die and from the second IF die and the second LK die, respectively; and

a pin dedicated to communication of parity bits from the first IF die and the first LK die and from the second IF die and the second LK die, respectively.

10 . The apparatus of claim 9 , further comprising a 32 bit burst length channel coupled to the first bus and the second bus, wherein 16 bits of the channel are received from the first IF die and the first LK die via the first bus and 16 bits of the channel are received from the second IF die and the second LK die via the second bus.

11 . The apparatus of claim 10 , wherein the channel is configured to communicate data from the first IF die and the first LK die to a host and from the second IF die and the second LK die to the host.

12 . The apparatus of claim 7 , wherein the first IF die, the first LK die, the second IF die, and the second LK die comprise a memory device.

13 . The apparatus of claim 12 , wherein the first IF die and the first LK die comprise a first memory component of the memory device and the second IF die and the second LK die comprise a second memory component of the memory device.

14 . The apparatus of claim 7 , wherein each pair of bits of the first plurality of subsets of bits and each pair of bits of the second plurality of subsets of bits include a respective symbol of the BCH error correction and a failure on a single LDIO line of the first plurality of LDIO lines and the second plurality of LDIO lines corresponds to at most two symbol errors.

15 . An apparatus, comprising:

control circuitry configured to:

partition a first plurality of bits of a memory transfer block (MTB) into a first plurality of subsets of bits;

partition a second plurality of bits of the MTB into a second plurality of subsets of bits;

generate symbols corresponding to respective pairs of bits of the MTB, wherein the first plurality of subsets of bits and the second plurality of subsets of bits each include two symbols;

communicate the plurality of pairs of bits of the MTB from a linked (LK) die to an interface (IF) die via a plurality of linked die input/output (LDIO) lines, wherein two pairs of bits of the plurality of pairs of bits are distributed to each LDIO line of the plurality of LDIO lines;

map the plurality of pairs of bits to pins of a data bus coupled to the IF die, wherein both of the two pairs of bits for each of the plurality of LDIO lines are mapped to the same pin of the data bus; and

responsive to a failed communication of the MTB, performing a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the MTB, wherein each of the first plurality of subsets of bits and the second plurality of subsets of bits include two pairs of bits, wherein each pair of bits is a respective symbol for the BCH error correction.

16 . The apparatus of claim 15 , further comprising:

a Compute Express Link (CXL) compliant memory system comprising:

a first linked (LK) die and a first interface (IF) die coupled to the first LK die; and

a second LK die and a second IF die coupled to the second IF die, wherein the control circuitry is further configured to:

subsequent to partitioning the first plurality of bits, communicate the MTB from the first LK die to the first IF die; and

subsequent to partitioning the second plurality of bits, communicate the MTB from the second LK die to the second IF die.

17 . The apparatus of claim 16 , wherein the CXL compliant memory system further comprises a first plurality of LK die input/output (LDIO) lines and a second plurality of LDIO lines, wherein the control circuitry is further configured to:

communicate the first plurality of subsets of bits via the first plurality of LDIO lines coupling the first LK die to the first IF die; and

communicate the second plurality of subsets of bits via the second plurality of LDIO lines coupling the second LK die to the second IF die.

18 . The apparatus of claim 15 , wherein bits of the first plurality of bits and bits of the second plurality of bits are numbered and the control circuitry is further configured to:

pair bits of the first plurality of bits that have the same number, wherein the first plurality of bits is partitioned into the first plurality of subsets of bits based on the paired bits of the first plurality of bits;

pair bits of the second plurality of bits that have the same number, wherein the second plurality of bits is partitioned into the second plurality of subsets of bits based on the paired bits of the second plurality of bits;

map each respective first subset of bits of the first plurality to one of a first plurality of linked (LK) die input/output (LDIO) lines via which the MTB communicated from a first LK die of a Compute Express Link (CXL) compliant memory system to a first interface (IF) die of the CXL compliant memory system; and

map each respective second subset of bits of the second plurality to one of a second plurality of LDIO lines via which the MTB communicated from a second LK die of a CXL compliant memory system to a second IF die of the CXL compliant memory system.

19 . The apparatus of claim 18 , wherein the control circuitry is further configured to perform the BCH error correction on the MTB in response to a failed communication of one of the first plurality of subsets of bits or the second plurality of subsets of bits via an LDIO line to which the subset of bits is mapped.

20 . The apparatus of claim 15 , wherein the MTB comprises a codeword for the BCH error correction, wherein the codeword corresponds to a quantity of bits of the MTB.