Digital quadrature clock for low jitter applications
Presented are systems and methods for generating quadrature clock signals for high-speed signal processing and similar applications. In various embodiments, a first input signal is rotated by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal. A second input signal that is 180 degrees out-of-phase with the first signal is rotated by a second phase angle such as to produce a second rotated signal. The unaltered first input signal and the phase-shifted second signal are then combined to derive an interpolated signal. This interpolated signal may be used to generate a second quadrature clock signal. As a result, the presented systems and methods effectively addresses the challenges of low-jitter, high-accuracy clock signal generation in applications such as SERDES and other systems that require precise timing signals, thereby ensuring enhanced system performance, while reducing complexity and power consumption.
1 . A quadrature clock generation method comprising:
rotating a first input signal by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal;
rotating a second input signal by a second phase angle to obtain a second rotated signal, the second input signal being 180 degrees out-of-phase with the first input signal;
combining the first input signal and the second rotated signal to obtain an interpolated signal using an interpolation circuit;
using the interpolated signal to obtain a second quadrature clock signal;
wherein obtaining the first rotated signal comprises using a first set of inverters to generate the first quadrature clock signal;
wherein obtaining the second quadrature clock signal comprises using a second set of inverters comprising the interpolation circuit; and
wherein the method comprises using a third set of inverters to match a delay caused by the second set of inverters.
2 . The quadrature clock generation method according to claim 1 , wherein at least one of the first or second input signals is generated by a voltage-controlled oscillator circuit.
3 . The quadrature clock generation method according to claim 1 , wherein the first phase angle is between 45 degrees and 135 degrees inclusive.
4 . The quadrature clock generation method according to claim 1 , wherein at least one of the first and second set of inverters are cascaded.
5 . The quadrature clock generation method according to claim 1 , wherein the first input signal is delayed by one-fourth of a clock period.
6 . The quadrature clock generation method according to claim 1 , further comprising using one or more dummy inverters to equalize a fanout.
7 . A quadrature clock generation circuit comprising:
a first inverter circuit configured to receive a first input signal and, in response to receiving the first input signal, to rotate the first input signal by a first phase angle to obtain a first rotated signal, which first rotated signal represents a first quadrature clock signal;
a second inverter circuit configured to receive a second input signal and, in response to receiving the second input signal, to rotate the second input signal by a second phase angle to obtain a second rotated signal, the second input signal being 180 degrees out-of-phase with the first input signal;
an interpolation circuit that combines the first input signal with the second rotated signal to obtain a second quadrature clock signal; and
a third inverter circuit configured to match a delay caused by the interpolation circuit.
8 . The quadrature clock generation circuit according to claim 7 , wherein the interpolation circuit comprises an averaging circuit configured to average the first input signal and the second rotated signal.
9 . The quadrature clock generation circuit according to claim 8 , wherein the averaging circuit is implemented with CMOS technology.
10 . The quadrature clock generation circuit according to claim 7 further comprising a voltage-controlled oscillator (VCO) circuit, wherein at least one of the first or second input signals is configured to be generated by the VCO circuit.
11 . The quadrature clock generation circuit according to claim 10 , wherein the VCO circuit is an LC VCO circuit.
12 . The quadrature clock generation circuit according to claim 7 , further comprising a buffer configured to balance a load of at least one of the first inverter circuit or the second inverter circuit.
13 . The quadrature clock generation circuit according to claim 7 , wherein at least one of the first inverter circuit or the second inverter circuit comprises at least one dummy inverter to equalize fanouts.
14 . The quadrature clock generation circuit according to claim 7 , wherein the first inverter circuit or the second inverter circuit are cascaded.
15 . The quadrature clock generation circuit according to claim 7 , wherein the first phase angle is between 45 degrees and 135 degrees inclusive.
16 . The quadrature clock generation circuit according to claim 7 , wherein the first and second input signals comprise at least one of a sinusoidal waveform or a rectangular waveform.