Tranceivers, method and network device implementing a phase interpolator core and lc tank for frequency-dependent impedance tuning
A transceiver for a network device includes clock-data recovery (CDR) circuitry that operates based on an input clock associated with a transmitted signal received by the transceiver. The CDR circuitry includes a phase interpolator (PI) core configured to process a plurality of phases of an the input clock, an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance, and control circuitry configured to tune the frequency-dependent impedance based on a frequency of the input clock.
1 . A transceiver for a network device including clock-data recovery (CDR) circuitry that operates based on an input clock associated with a transmitted signal received by the transceiver, the CDR circuitry comprising:
a phase interpolator (PI) core configured to process a plurality of phases of the input clock;
an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance; and
control circuitry configured to detect the output voltage, and, based on the output voltage, tune the frequency-dependent impedance to maximize the output voltage for a frequency of the input clock.
2 . The transceiver of claim 1 , wherein the control circuitry is configured to i) based on the output voltage, determine whether the frequency-dependent impedance is tuned to maximize the output voltage for the frequency of the input clock, and ii) tune the frequency-dependent impedance in response to the frequency-dependent impedance not being tuned to maximize the output voltage.
3 . A transceiver for a network device including clock-data recovery (CDR) circuitry that operates based on an input clock associated with a transmitted signal received by the transceiver, the CDR circuitry comprising:
a phase interpolator (PI) core configured to process a plurality of phases of the input clock;
an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance, wherein the LC tank comprises
a first branch and a second branch, each of the first branch and the second branch comprising an inductor and a plurality of capacitors, and
a plurality of switches, wherein each respective switch of the plurality of switches is arranged between a respective capacitor of the first branch and a respective capacitor of the second branch; and
control circuitry configured to tune the frequency-dependent impedance based on a frequency of the input clock.
4 . The transceiver of claim 3 , wherein the control circuitry is configured to tune the frequency-dependent impedance by opening or closing switches of the plurality of switches.
5 . The transceiver of claim 4 , wherein the control circuitry comprises peak detector circuitry configured to determine a magnitude of the output voltage.
6 . The transceiver of claim 5 , wherein the peak detector circuitry comprises:
an operational amplifier configured to charge a capacitor based on the output current and the frequency-dependent impedance; and
a register configured to store at least one voltage of the capacitor, wherein determining the magnitude of the output voltage is based on the at least one voltage of the capacitor.
7 . The transceiver of claim 6 , wherein the control circuitry is further configured to:
implement a plurality of configurations of the plurality of switches, each respective one of the plurality of configurations corresponding to a respective frequency-dependent impedance; and
determine a maximum voltage of the capacitor based on inspecting the at least one voltage of the capacitor for each configuration of the plurality of configurations.
8 . The transceiver of claim 7 , wherein the control circuitry is further configured to implement a particular configuration of the plurality of configurations to cause the LC tank to provide the magnitude of the output voltage as a maximum output voltage.
9 . The transceiver of claim 3 , wherein:
the PI core is configured to receive a differential input and provide a differential output; and
the first branch and the second branch of the LC tank are coupled to respective differential legs of the PI core.
10 . A transceiver for a network device including clock-data recovery (CDR) circuitry that operates based on an input clock associated with a transmitted signal received by the transceiver, the CDR circuitry comprising:
a phase interpolator (PI) core configured to process a plurality of phases of the input clock;
an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance;
a cross latch coupled to the LC tank to tune a quality factor of the frequency-dependent impedance; and
control circuitry configured to tune the frequency-dependent impedance based on a frequency of the input clock.
11 . The transceiver of claim 10 , wherein:
the cross latch comprises a current mirror; and
the control circuitry is further configured to tune the quality factor of the frequency-dependent impedance by controlling a current flowing through the current mirror.
12 . A method for operating a transceiver for a network device, the method comprising:
processing, using a phase interpolator (PI) core, a plurality of phases of an input clock;
converting, using an inductor-capacitor (LC) tank, an output current of the PI core to an output voltage based on a frequency-dependent impedance;
detect the output voltage; and
based on the output voltage, tuning, using control circuitry, the frequency-dependent impedance to maximize the output voltage for a frequency of the input clock.
13 . The method of claim 12 , where the LC tank includes a first branch and a second branch, each of the first branch and the second branch comprising an inductor and a plurality of capacitors, and where the LC tank further includes a plurality of switches, each respective switch of the plurality of switches being arranged between a respective capacitor of the first branch and a respective capacitor of the second branch, the method further comprising:
tuning, using the control circuitry, the frequency-dependent impedance by opening or closing switches of the plurality of switches.
14 . The method of claim 13 , where the control circuitry includes peak detector circuitry, the method further comprising:
determining, using the peak detector circuitry, a magnitude of the output voltage.
15 . The method of claim 14 , where the peak detector circuitry includes a register and an operational amplifier configured to charge a capacitor based on the output current and the frequency-dependent impedance, the method further comprising:
storing, using the register, at least one voltage of the capacitor; and
determining the magnitude of the output voltage based on the at least one voltage of the capacitor.
16 . The method of claim 15 , further comprising:
implementing, using the control circuitry, a plurality of configurations of the plurality of switches, each respective one of the plurality of configurations corresponding to a respective frequency-dependent impedance; and
determining a maximum voltage of the capacitor based on inspecting, using the control circuitry, the at least one voltage of the capacitor for each configuration of the plurality of configurations.
17 . The method of claim 16 , further comprising implementing, using the control circuitry, a particular configuration of the plurality of configurations to cause the LC tank to provide the magnitude of the output voltage as a maximum output voltage.
18 . The method of claim 13 , where the first branch and the second branch of the LC tank are coupled to respective differential legs of the PI core; wherein:
processing the plurality of phases of the input clock comprises receiving differential inputs from the input clock and providing differential outputs to the first branch and the second branch of the LC tank, respectively.
19 . The method of claim 12 , further comprising tuning, using a cross latch coupled to the LC tank, a quality factor of the frequency-dependent impedance.
20 . The method of claim 19 , where the cross latch includes a current mirror; wherein:
tuning, using the control circuitry, the frequency-dependent impedance comprises controlling a current flowing through the current mirror.
21 . A network device including a transceiver and a host, the transceiver comprising:
a phase interpolator (PI) core configured to process a plurality of phases of an input clock;
an inductor-capacitor (LC) tank configured to convert an output current of the PI core to an output voltage based on a frequency-dependent impedance;
control circuitry configured to tune the frequency-dependent impedance based on a frequency of the input clock; and
processing circuitry configured to process a signal based on the output voltage of the PI core and to provide the processed signal to the host.