Device for counteracting side-channel attacks
A device for counteracting side-channel attacks (SCA), including a machine learning unit (MLU) that is connectable to a cryptographic core. The MLU includes: a feature extractor unit configured to extract selected information-sensitive signals from the cryptographic core and to generate machine learning features based on the selected information-sensitive signals; and a machine learning-based power estimator unit configured to output cumulative information-sensitive energy based on the generated machine learning features. The device further includes a power compensation unit that is configured to cancel out the cumulative information-sensitive energy so as to counteract side-channel attacks (SCA).
1 . A device for counteracting side-channel attacks (SCA), comprising:
a machine learning unit (MLU) that is connectable to a cryptographic core, wherein the MLU:
extracts information-sensitive signals from the cryptographic core and to generate machine learning features based on the information-sensitive signals; and
outputs cumulative information-sensitive energy based on the generated machine learning features; and
cancels out the cumulative information-sensitive energy so as to counteract side-channel attacks (SCA).
2 . The device according to claim 1 , wherein the information-sensitive signals from the cryptographic core are selected based on multiplexing and/or clock gating logic.
3 . The device according to claim 1 , wherein the MLU adopts a linear regression model.
4 . The device according to claim 3 , wherein the linear regression model is based on equation (1) as follows:
y
(
w
,
x
)
=
w
0
+
∑
k
=
1
K
∑
d
=
1
D
w
k
d
x
k
d
Eq
.
(
1
)
where:
x are the generated machine learning features from the MLU,
w are pre-trained machine learning model parameters,
K represents a number of subkey blocks, and
D represents selected one or more of the generated machine learning features.
5 . The device according to claim 4 , wherein the pre-trained machine learning model parameters are updatable and subsequently mappable into the linear regression model to implement a hardware patch.
6 . The device according to claim 1 , wherein the MLU is connectable to a supply source, and wherein MLU is configured to draw an equivalent energy from the supply source to cancel out the cumulative information-sensitive energy.
7 . The device according to claim 1 , wherein the MLU comprises an N-bit capacitive digital-to-analog converter standard cell comprising N binary scaled gate clusters.
8 . The device according to claim 7 , wherein N is 10, and wherein the cumulative information-sensitive energy is expressed as 10-bit control signals.
9 . The device according to claim 7 , wherein a transition and an energy contribution of each of the gate clusters is enabled if a corresponding input bit from the MLU is 1.