Multi-tap decision feedback equalizer (DFE) training in a memory physical (PHY) layer
Technologies for optimizing multi-tap Decision Feedback Equalizer (DFE) training in the memory physical (PHY) layer may be described. A receiver circuit includes analog and digital circuitry. The analog circuitry includes a single de-serializer and a set of DFE taps. The digital circuitry includes a register to store a copy of a set of training patterns. The digital circuitry performs byte alignment using a first training pattern. The digital circuitry may match error bits received from the single de-serializer with data bits of the copy of the set of training patterns. The digital circuitry may calibrate the set of DFE taps using the error bits and the data bits.
1 . A receiver circuit of a physical layer (PHY) of a memory controller, the receiver circuit comprising;
a data path configured to receive a signal from a dynamic random access memory (DRAM) device at a data pin over a channel, the data path comprising a plurality of Decision Feedback Equalizer (DFE) taps and only one de-serializer block configured to produce received data; and
a digital logic coupled to the data path, wherein the digital logic is configured to perform byte alignment by comparing the received data with first data stored in a register of the digital logic, wherein the plurality of DFE taps is calibrated by comparing the received data with second data stored in the register, wherein the digital logic comprises a counter configured to select portions of the second data for comparisons with the received data.
2 . The receiver circuit of claim 1 , wherein the first data comprises a toggling pattern.
3 . The receiver circuit of claim 1 , wherein the second data comprises a plurality of predefined patterns.
4 . The receiver circuit of claim 1 , wherein the plurality of DFE taps is calibrated by a Sign-Sign Least Mean Squares (SSLMS) algorithm.
5 . The receiver circuit of claim 1 , wherein the receiver circuit is configured to continuously read from a first-in-first-out (FIFO) of the DRAM device, the FIFO storing a plurality of predefined patterns, wherein the register is configured to store a copy of the plurality of predefined patterns.
6 . The receiver circuit of claim 1 , wherein the data path further comprises:
an analog front-end (AFE) circuit configured to receive the signal from the DRAM device;
a data slicer;
an error slicer; and
a multiplexer coupled to the data slicer and the error slicer, wherein the multiplexer is configured to select an output of the error slicer in a training mode in which the plurality of DFE taps is calibrated.
7 . The receiver circuit of claim 1 , wherein the data path further comprises:
an analog front-end (AFE) circuit configured to receive the signal from the DRAM device;
a first data slicer;
a second data slicer;
a first error slicer;
a second error slicer;
a first multiplexer coupled to the first data slicer and the first error slicer; and
a second multiplexer coupled to the second data slicer and the second error slicer, wherein the first multiplexer is configured to select an output of the first error slicer and the second multiplexer is configured to select an output of the second error slicer in a training mode in which the plurality of DFE taps is calibrated, wherein the de-serializer block is a 2:N de-serializer block, where N is a positive integer greater than two.
8 . The receiver circuit of claim 1 , wherein the digital logic further comprises:
a Sign-Sign Least Mean Squares (SSLMS) core that implements an SSLMS algorithm;
an alignment logic configured to perform the byte alignment, the alignment logic is configured to output the received data, and an indicator that indicates that the received data is byte aligned, wherein the received data comprises error bits received from the de-serializer block; and
a matching logic configured to receive the received data and the indicator from the alignment logic, the matching logic is configured to match the error bits with data bits of the second data stored in the register, the matching logic is configured to output cycle-to-cycle matched error bits and data bits to the SSLMS core.
9 . A receiver circuit comprising:
analog circuitry comprising a single de-serializer and a plurality of Decision Feedback Equalizer (DFE) taps, wherein, during a training mode of the receiver circuit, the analog circuitry is configured to receive a first training pattern in a first stage of the training mode and a plurality of training patterns in a second stage of the training mode; and
digital circuitry coupled to the analog circuitry, the digital circuitry comprising a register configured to store a copy of the plurality of training patterns, wherein the digital circuitry is configured to perform byte alignment using the first training pattern in the first stage, wherein, in the second stage, the digital circuitry is configured to match error bits received from the single de-serializer with data bits of the copy of the plurality of training patterns, and wherein, in the second stage, the digital circuitry is configured to calibrate the plurality of DFE taps using the error bits and the data bits.
10 . The receiver circuit of claim 9 , wherein the digital circuitry further comprises:
a Sign-Sign Least Mean Squares (SSLMS) core that implements an SSLMS algorithm to calibrate the plurality of DFE taps;
an alignment logic configured to perform the byte alignment, the alignment logic is configured to output the error bits and a byte-aligned indicator; and
matching logic to receive the error bits and the byte-aligned indicator from the alignment logic, the matching logic to match the error bits with the data bits of the copy of the plurality of training patterns stored in the register, the matching logic is configured to output the matching error bits and data bits to the SSLMS core.
11 . The receiver circuit of claim 9 , wherein the first training pattern comprises a toggling sequence of bits, and wherein the plurality of training patterns comprises different predefined sequences of bits.
12 . The receiver circuit of claim 9 , wherein the analog circuitry further comprises:
an analog front-end (AFE) circuit configured to receive a signal from a dynamic random access memory (DRAM) device;
a data slicer;
an error slicer; and
a multiplexer coupled to the data slicer and the error slicer, wherein the multiplexer configured is to select an output of the error slicer in a training mode in which the plurality of DFE taps is calibrated.
13 . The receiver circuit of claim 9 , wherein the analog circuitry further comprises:
an analog front-end (AFE) circuit configured to receive a signal from a dynamic random access memory (DRAM) device;
a first data slicer;
a second data slicer;
a first error slicer;
a second error slicer;
a first multiplexer coupled to the first data slicer and the first error slicer; and
a second multiplexer coupled to the second data slicer and the second error slicer, wherein the first multiplexer is configured to select an output of the first error slicer and the second multiplexer is configured to select an output of the second error slicer in a training mode in which the plurality of DFE taps is calibrated, wherein the de-serializer block is a 2:N de-serializer block, where N is a positive integer greater than two.
14 . A system comprising:
a dynamic random access memory (DRAM) device comprising a first-in-first-out (FIFO) configured to store a plurality of training patterns, the DRAM device is configured to send first data bits of the plurality of training patterns; and
a memory controller coupled to the DRAM device via a channel, wherein the memory controller comprises a register configured to store a copy of the plurality of training patterns, wherein the memory controller comprises:
analog circuitry comprising a single de-serializer and a plurality of Decision Feedback Equalizer (DFE) taps, the single de-serializer is configured to only provide error bits corresponding to the first data bits received from the DRAM device; and
digital circuitry coupled to the analog circuitry, wherein the digital circuitry is configured to perform byte alignment using a toggling pattern, and wherein the digital circuitry is configured to calibrate the plurality of DFE taps using the error bits received from the single de-serializer and matching second data bits of the copy of the plurality of training patterns stored in the register.
15 . The system of claim 14 , wherein the digital circuitry comprises a counter configured to sequentially select each training pattern of the copy of the plurality of training patterns stored in the register.
16 . The system of claim 14 , wherein the digital circuitry comprises:
a Sign-Sign Least Mean Squares (SSLMS) core that implements an SSLMS algorithm to calibrate the plurality of DFE taps;
an alignment logic configured to perform the byte alignment, the alignment logic is configured to output the error bits and a byte-aligned indicator; and
a matching logic configured to receive the error bits and the byte-aligned indicator from the alignment logic, the matching logic is configured to match the error bits with the second data bits of the copy of the plurality of training patterns stored in the register, the matching logic is configured to output the error bits and the matching second data bits.
17 . The system of claim 14 , wherein the analog circuitry further comprises:
an analog front-end (AFE) circuit configured to receive a signal from the DRAM device;
a first data slicer;
a second data slicer;
a first error slicer;
a second error slicer;
a first multiplexer coupled to the first data slicer and the first error slicer; and
a second multiplexer coupled to the second data slicer and the second error slicer, wherein the first multiplexer is configured to select an output of the first error slicer and the second multiplexer is configured to select an output of the second error slicer in a training mode in which the plurality of DFE taps is calibrated, wherein the de-serializer block is a 2:N de-serializer block, where N is a positive integer greater than two.