Solid-state imaging element, method for controlling solid-state imaging element, and electronic device

1 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal; and

a second sample hold circuit that holds the second pixel signal, wherein the first and second sample hold circuits each include:

a first capacitor;

a second capacitor with one end connected to the first capacitor;

a first sampling transistor that opens or closes a path between a connection node of the first and second capacitors and the pixel signal generation circuit;

a pre-amplification transistor; and

a second sampling transistor that opens or closes a path between an other end of the second capacitor and a predetermined reference voltage.

2 . The solid-state imaging circuit according to claim 1 , wherein one of the first and second sample hold circuits further includes a reading circuit for sequentially reading the first and second pixel signals, and

the first and second sample hold circuits share the reading circuit.

3 . The solid-state imaging circuit according to claim 1 , wherein the first and second sample hold circuits each include:

a first capacitor;

a first sampling transistor that opens or closes a path between one end of the first capacitor and the pixel signal generation circuit;

a second capacitor; and

a second sampling transistor that opens or closes a path between one end of the second capacitor and the pixel signal generation circuit.

4 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal; and

a second sample hold circuit that holds the second pixel signal,

wherein the first and second sample hold circuits each include:

a first capacitor;

a first sampling transistor that opens or closes a path between one end of the first capacitor and the pixel signal generation circuit;

a second capacitor; and

a second sampling transistor that opens or closes a path between one end of the first capacitor and one end of the second capacitor.

5 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal; and

a second sample hold circuit that holds the second pixel signal,

wherein the first and second sample hold circuits each include:

a first capacitor with one end connected to the pixel signal generation circuit;

a second capacitor;

a first sampling transistor that opens or closes a path between an other end of the first capacitor and one end of the second capacitor; and

a second sampling transistor that opens or closes a path between one end of the second capacitor and a predetermined power supply voltage.

6 . The solid-state imaging circuit according to claim 1 , wherein the first and second sample hold circuits each include:

first and second capacitive capacitors with one ends connected in common to the pixel signal generation circuit;

a first sampling transistor that opens or closes a path between the other end of the first capacitor and a predetermined node;

a second sampling transistor that opens or closes a path between the other end of the second capacitor and the predetermined node; and

a third sampling transistor that opens or closes a path between the predetermined node and a predetermined power supply voltage.

7 . The solid-state imaging circuit according to claim 1 , further comprising a vertical scanning circuit that drives a predetermined number of pixels,

wherein the pixel signal generation circuit and the first and second sample hold circuits are disposed in each of the pixels, and

the vertical scanning circuit simultaneously exposes all the pixels, holds the first and second pixel signals, and outputs the first and second pixel signals for each row.

8 . The solid-state imaging circuit according to claim 7 , wherein the first and second pixel signals each include a reset level and a signal level, and the vertical scanning circuit outputs the reset level before exposure.

9 . The solid-state imaging circuit according to claim 7 , wherein the vertical scanning circuit outputs the first and second pixel signals during exposure.

10 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal;

a vertical scanning circuit that drives a predetermined number of pixels,

wherein the pixel signal generation circuit and the first and second sample hold circuits are disposed in each of the pixels,

the vertical scanning circuit simultaneously exposes all the pixels, holds the first and second pixel signals, and outputs the first and second pixel signals for each row, and

the vertical scanning circuit outputs the first and second pixel signals during exposure; and

a second sample hold circuit that holds the second pixel signal an exposure time control circuit that controls an exposure time based upon the first and second pixel signals outputted during exposure.

11 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal;

a vertical scanning circuit that drives a predetermined number of pixels,

wherein the pixel signal generation circuit and the first and second sample hold circuits are disposed in each of the pixels,

the vertical scanning circuit simultaneously exposes all the pixels, holds the first and second pixel signals, and outputs the first and second pixel signals for each row, and

the vertical scanning circuit outputs the first and second pixel signals during exposure;

an analog-digital converter that performs analog-digital conversion on the first and second pixel signals; and

a gain control circuit that controls an analog gain of the analog-digital converter based upon the first and second pixel signals outputted during exposure.

12 . The solid-state imaging circuit according to claim 1 , wherein a first part of the pixel signal generation circuit is disposed in a first chip, and a second part of the pixel signal generation circuit and the first and second sample hold circuits are disposed in a second chip.

13 . A solid-state imaging circuit comprising:

a pixel signal generation circuit that generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer;

a first sample hold circuit that holds the first pixel signal; and

a second sample hold circuit that holds the second pixel signal, wherein

a first part of the pixel signal generation circuit and parts of the first and second sample hold circuits are disposed in a first chip, and other parts of the first and second sample hold circuits are disposed in a second chip.

14 . The solid-state imaging circuit according to claim 1 , wherein the pixel signal generation circuit and the first and second sample hold circuits each include a source follower circuit.

15 . The solid-state imaging circuit according to claim 1 , wherein the pixel signal generation circuit and the first and second sample hold circuits each include a source ground circuit.

16 . The solid-state imaging circuit according to claim 1 , wherein the first and second sample hold circuits each include a predetermined number of capacitors, and

each of the capacitors is one of a MIM (Metal-Insulator-Metal) capacitor, a MOM (Metal-Oxide-Metal) capacitor, a MOS (Metal-Oxide-Semiconductor) capacitor, a DRAM (Dynamic Random Access Memory) cell capacitor, and CDTI (Capacitive Deep Trench Isolation).

17 . An electronic device comprising the solid-state imaging circuit according to claim 1 .

18 . An electronic device comprising the solid-state imaging circuit according to claim 4 .

19 . An electronic device comprising the solid-state imaging circuit according to claim 5 .

20 . An electronic device comprising the solid-state imaging circuit according to claim 13 .