Oxide semiconductor device and oxide semiconductor memory device
A semiconductor device of embodiments includes: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing the third region; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a p-type semiconductor layer in contact with the third region and separated from the gate electrode, the first electrode, and the second electrode, the third region being provided between the p-type semiconductor layer and the gate electrode.
1 . A semiconductor device, comprising:
a first electrode;
a second electrode;
an oxide semiconductor layer provided between the first electrode and the second electrode, and the oxide semiconductor layer being in direct contact with the first electrode and the second electrode;
a gate electrode facing the oxide semiconductor layer;
a gate insulating layer provided between the gate electrode and the oxide semiconductor layer;
a p-type semiconductor layer surrounded by the oxide semiconductor layer in a cross section perpendicular to a first direction connecting the first electrode and the second electrode to each other, the p-type semiconductor layer being in contact with the oxide semiconductor layer, and separated from the gate electrode, the first electrode, and the second electrode;
a first insulating layer provided between the first electrode and the p-type semiconductor layer, and the first insulating layer being surrounded by the oxide semiconductor layer in a cross section perpendicular to the first direction; and
a second insulating layer provided between the second electrode and the p-type semiconductor layer, and the second insulating layer being surrounded by the oxide semiconductor layer in a cross section perpendicular to the first direction.
2 . The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer is n-type.
3 . The semiconductor device according to claim 1 ,
wherein a conduction band bottom energy of the p-type semiconductor layer is larger than a conduction band bottom energy of the oxide semiconductor layer,
the conduction band bottom energy of the oxide semiconductor layer is larger than a valence band top energy of the p-type semiconductor layer, and
the valence band top energy of the p-type semiconductor layer is larger than a valence band top energy of the oxide semiconductor layer.
4 . The semiconductor device according to claim 3 ,
wherein a difference between the conduction band bottom energy of the p-type semiconductor layer and the conduction band bottom energy of the oxide semiconductor layer is equal to or more than 0.25 eV.
5 . The semiconductor device according to claim 3 ,
wherein a difference between the conduction band bottom energy of the oxide semiconductor layer and the valence band top energy of the p-type semiconductor layer is equal to or more than 0.25 eV.
6 . The semiconductor device according to claim 1 ,
wherein the p-type semiconductor layer is electrically floating.
7 . The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer contains zinc (Zn), oxygen (O), and at least one element selected from a group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn).
8 . The semiconductor device according to claim 1 ,
wherein the p-type semiconductor layer contains silicon (Si).
9 . The semiconductor device according to claim 1 ,
wherein a p-type impurity concentration in the p-type semiconductor layer is equal to or more than 1×1018 atoms/cm3 and less than 8×1019 atoms/cm3.
10 . The semiconductor device according to claim 1 ,
wherein the gate electrode surrounds the oxide semiconductor layer.
11 . The semiconductor device according to claim 1 ,
wherein a length of the p-type semiconductor layer in the first direction connecting the first electrode and the second electrode to each other is shorter than a length of the gate electrode in the first direction.
12 . The semiconductor device according to claim 1 , further comprising:
a third insulating layer surrounded by the p-type semiconductor layer.
13 . A semiconductor memory device, comprising:
the semiconductor device according to claim 1 ; and
a capacitor electrically connected to the first electrode or the second electrode.