Semiconductor device and method for fabricating the same
A semiconductor device includes a lower structure; a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure; a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line; a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween.
1 . A semiconductor device, comprising:
a lower structure;
a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure;
a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line;
a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and
a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween
wherein the bridge horizontal layer and the horizontal layers are formed of a metal-based material, and
wherein the bridge horizontal layer directly and electrically connects the horizontal layers.
2 . The semiconductor device of claim 1 , wherein the bridge horizontal layer includes
a first edge contacting the vertical conductive line and
a second edge contacting the reservoir capacitor.
3 . The semiconductor device of claim 1 , wherein the reservoir capacitor includes:
a cylindrical first electrode coupled to the bridge horizontal layer;
a dielectric layer over the cylindrical first electrode; and
a second electrode over the dielectric layer.
4 . The semiconductor device of claim 1 , wherein the vertical conductive line includes a silicon-based material, a metal-based material, or a combination thereof.
5 . The semiconductor device of claim 1 , further comprising:
a low voltage node which is coupled to the vertical conductive line; and
a high voltage node which is coupled to the reservoir capacitor.
6 . A semiconductor device, comprising:
a memory cell array including a three-dimensional array of cell capacitors; and
a reservoir capacitor array which is horizontally spaced apart from the memory cell array and includes a three-dimensional array of reservoir capacitor structures,
wherein each of the reservoir capacitor structures includes:
a vertical conductive line;
a reservoir capacitor which is spaced apart from the vertical conductive line and has the same structure as structures of the cell capacitors;
a bridge horizontal layer oriented horizontally between the vertical conductive line and the reservoir capacitor; and
a pair of horizontal layers extending in a direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween
wherein the bridge horizontal layer and the horizontal layers are formed of a metal-based material, and
wherein the bridge horizontal layer directly and electrically connects the horizontal layers.
7 . The semiconductor device of claim 6 , wherein the bridge horizontal layer includes
a first edge contacting the vertical conductive line, and
a second edge contacting the reservoir capacitor.
8 . The semiconductor device of claim 6 , wherein each of the cell capacitors and the reservoir capacitors includes:
a cylindrical first electrode;
a dielectric layer over the cylindrical first electrode; and
a second electrode over the dielectric layer.
9 . The semiconductor device of claim 6 , wherein the vertical conductive line includes a silicon-based material, a metal-based material, or a combination thereof.
10 . The semiconductor device of claim 6 , further comprising:
a low voltage node which is coupled to the vertical conductive line; and
a high voltage node which is coupled to the reservoir capacitor.
11 . The semiconductor device of claim 6 , wherein the memory cell array includes:
a vertical bit line;
a cell horizontal layer which is oriented horizontally between the bit line and the cell capacitors;
a pair of word lines extending in a direction intersecting the cell horizontal layer with the cell horizontal layer interposed therebetween; and
a gate dielectric layer between the word lines and the cell horizontal layer.
12 . The semiconductor device of claim 11 , wherein the cell horizontal layer includes monocrystalline silicon, polysilicon or an oxide semiconductor.
13 . The semiconductor device of claim 6 , further comprising:
a peripheral circuit portion disposed at a lower level than the memory cell array and the reservoir capacitor array.
14 . The semiconductor device of claim 6 , wherein the cell capacitors and the reservoir capacitors are disposed at the same horizontal level.