Semiconductor structure having a ladder contact structure
The present disclosure discloses a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a plurality of word lines and a plurality of bit lines; ladder structure, including multiple steps, each step includes a first part which extends along the first direction, and a second part which extends along the second direction; a plurality of electrical contact structures, the electrical contact structures is disposed on the top surfaces of a portion of the first part and the second part of the steps, and the electrical contact structures are electrically connected to the word lines or bit lines.
1 . A semiconductor structure, comprising:
a plurality of word lines ( 11 ) and a plurality of bit lines ( 12 ), wherein the plurality of word lines ( 11 ) extends in a direction which is different from a direction the plurality of bit lines ( 12 ) extends;
a ladder structure ( 1 ), wherein the ladder structure ( 1 ) comprises multiple steps ( 101 ), wherein the steps ( 101 ) comprise a first part ( 121 ) and a second part ( 122 ) that are connected, wherein the first part extends in a first direction (X), the second part ( 122 ) extends in a second direction (Y), and the first direction (X) is different from the second direction (Y); and
a plurality of electrical contact structures ( 102 ), wherein the plurality of electrical contact structures ( 102 ) is disposed on top surfaces of a portion of the first part ( 121 ) and the second part ( 122 ) of the steps ( 101 ), and wherein the plurality of electrical contact structures ( 102 ) is in contact with the plurality of word lines ( 11 ) or the plurality of bit lines ( 12 ).
2 . The semiconductor structure according to claim 1 , wherein a portion of the steps ( 101 ) further comprises: a third part ( 123 ) connected to the second part ( 122 ), wherein the third part ( 123 ) extends along a third direction (W), wherein the third direction (W) is different from the second direction (Y), and wherein the plurality of electrical contact structures ( 102 ) is also disposed on top surfaces of the third part ( 123 ) of a portion of the steps ( 101 ).
3 . The semiconductor structure according to claim 2 , wherein the third direction (W) is parallel to the first direction (X).
4 . The semiconductor structure according claim 1 , wherein each of the steps ( 101 ) comprises a third part ( 123 ), a first part ( 121 ), a second part ( 122 ), and wherein the first part ( 121 ) and the second part ( 122 ) connect to the third part ( 123 ) sequentially to make steps ( 101 ) form U-shapes.
5 . The semiconductor structure according to claim 1 , wherein the steps ( 101 ) form a closed ring.
6 . The semiconductor structure according to claim 5 , wherein the closed ring is a closed rectangle, wherein the steps ( 101 ) comprise: a first part ( 121 ), a second part ( 122 ), a third part ( 123 ), and a fourth part ( 124 ),) connected in sequence, and wherein the third part ( 123 ) extends along the first direction (X), the fourth part ( 124 ) extends along the second direction (Y), and wherein the plurality of electrical contact structure ( 102 ) is disposed on top surfaces of the third part ( 123 ) and the fourth part ( 124 ) of the steps ( 101 ).
7 . The semiconductor structure according to claim 1, 2 or 5 , wherein the plurality of electrical contact structures ( 102 ) comprises:
a contact layer ( 111 ), where the contact layer ( 111 ) is disposed on top surfaces of a portion of the steps ( 101 );
a connecting column ( 112 ), wherein the connecting column ( 112 ) is in contact with the contact layer ( 111 ), wherein a top surface of the connecting column ( 112 ) is configured to be flush with the top surfaces of the plurality of steps ( 101 ), and wherein the ladder structure ( 1 ) exposes end surfaces of the contact layer ( 111 ) away from the connection column ( 112 ), wherein the exposed end surfaces are in contact with one of the plurality of bit lines ( 12 ) or the plurality of word lines ( 11 ).
8 . The semiconductor structure according to claim 7 , further comprising: a plurality of lead-out structures ( 103 ), wherein the lead-out structures ( 103 ) are electrically connected to the top surface of the connection column ( 112 ).
9 . The semiconductor structure according to claim 1 , further comprising: an isolation structure ( 104 ), wherein the isolation structure ( 104 ) is located between two adjacent ones of the plurality of electrical contact structures ( 102 ), and wherein the isolation structure ( 104 ) isolates two adjacent ones of the plurality of electrical contact structures ( 102 ).
10 . The semiconductor structure according to claim 1 , wherein the plurality of bit lines ( 12 ) or the plurality of word lines ( 11 ) is electrically connected to one of the plurality of electrical contact structures ( 102 ) corresponding to the first part ( 121 ) or the second part ( 122 ).