Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction, an active pattern on the cell block region, a bit line provided on the active pattern and extended in the first direction, a first insulating structure in contact with the bit line, and a contact plug electrically connected to the bit line. The bit line may include a first curved portion, a first linear portion connected to the first curved portion, and a first intervening portion connected to the first curved portion. The contact plug may be overlapped with the first curved portion.
1 . A semiconductor device, comprising:
a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction;
an active pattern on the cell block region;
a bit line on the active pattern and extending in the first direction;
a first insulating structure in contact with the bit line; and
a contact plug electrically connected to the bit line,
wherein, as seen in plan view, the bit line comprises a first curved portion, a first linear portion connected to a side of the first curved portion, and a first intervening portion having a first end connected to the side of the first curved portion and a second end connected to an end of the first insulating structure, and
the contact plug overlaps with the first curved portion.
2 . The semiconductor device of claim 1 , wherein a width of the first curved portion is larger than a width of the first linear portion.
3 . The semiconductor device of claim 1 , wherein a top surface of the first insulating structure is coplanar with a top surface of the bit line.
4 . The semiconductor device of claim 1 , wherein
the bit line further comprises a second curved portion, a second intervening portion connected to the second curved portion, and a second linear portion connected to the second curved portion, and
the first insulating structure is interposed between the first intervening portion and the second linear portion.
5 . The semiconductor device of claim 4 , wherein
the active pattern comprises a first active pattern and a second active pattern, which are spaced apart from each other in a second direction crossing the first direction,
the first linear portion vertically overlaps with the first active pattern, and
the second linear portion vertically overlaps with the second active pattern.
6 . The semiconductor device of claim 4 , further comprising:
a second insulating structure interposed between the second intervening portion and the first linear portion.
7 . The semiconductor device of claim 1 , further comprising:
a bit line capping pattern on the bit line,
wherein the contact plug penetrates the bit line capping pattern and is connected to the first curved portion of the bit line.
8 . The semiconductor device of claim 1 , wherein a width of the first insulating structure is equal to a width of the first linear portion of the bit line.
9 . The semiconductor device of claim 1 , further comprising:
an outer spacer on an outer side surface of the bit line; and
an inner spacer on an inner side surface of the bit line,
wherein the contact plug is interposed between the outer spacer and the inner spacer.
10 . A semiconductor device, comprising:
a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction;
an active pattern on the cell block region;
a bit line on the active pattern and extending in the first direction;
a first insulating structure in contact with the bit line; and
a contact plug electrically connected to the bit line, wherein a top surface of the bit line is coplanar with a top surface of the first insulating structure,
wherein, as seen in plan view, the bit line comprises a first curved portion, a first linear portion connected to a side of the first curved portion, and a first intervening portion having a first end connected to the side of the first curved portion and a second end connected to an end of the first insulating structure.
11 . The semiconductor device of claim 10 , wherein a width of the first curved portion is larger than a width of the first linear portion.
12 . The semiconductor device of claim 10 , wherein the bit line further comprises a first protruding portion, and wherein the first curved portion connected to the first protruding portion, and the contact plug is connected to the first protruding portion.
13 . The semiconductor device of claim 12 , wherein the first protruding portion extends from the first curved portion toward the peripheral region.
14 . The semiconductor device of claim 12 , wherein
the bit line further comprises a second curved portion, a second intervening portion connected to the second curved portion, and a second linear portion connected to the second intervening portion, and
the first insulating structure is interposed between the first intervening portion and the second linear portion.
15 . The semiconductor device of claim 14 , further comprising:
a second insulating structure connected to the first linear portion and the second intervening portion.
16 . The semiconductor device of claim 12 , wherein the first protruding portion overlaps with the cell block region.
17 . The semiconductor device of claim 12 , wherein a width of the first protruding portion is smaller than a width of the first curved portion of the bit line.
18 . The semiconductor device of claim 12 , wherein a bottom surface of the contact plug is below a top surface of the first insulating structure.
19 . A semiconductor device, comprising:
a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction;
an active pattern on the cell block region; a bit line on the active pattern and extending in the first direction;
an insulating structure in contact with the bit line;
a contact plug electrically connected to the bit line;
an outer spacer on an outer side surface of the bit line; and
an inner spacer on an inner side surface of the bit line,
wherein a top surface of the bit line is coplanar with a top surface of the insulating structure,
wherein, as seen in plan view, the bit line comprises a first curved portion, a first linear portion connected to a side of the first curved portion, and a first intervening portion having a first end connected to the side of the first curved portion and a second end connected to an end of the insulating structure, and
the insulating structure is interposed between the outer spacer and the inner spacer.
20 . The semiconductor device of claim 19 , wherein the contact plug is connected to the first curved portion.